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| 1/128 june 2003 rev. 2.0 psd3251f 8032 mcu with programmable logic features summary the psd3251f device combines a flash psd architecture with an 8032 microcontroller core. the psd3251f device of flash psds feature dual banks of flash memory, sram, general purpose i/o and programmable logic, supervi- sory functions and access via i 2 c, adc, and an on-board 8032 microcontroller core, with two uarts, three 16-bit timer/counters and two external interrupts. as with other flash psd families, the psd3251f device are also in-sys- tem programmable (isp) via a jtag isp inter- face. large 2kbyte sram with battery back-up option dual bank flash memories ? 64kbyte main flash memory ? 16kbyte secondary flash memory content security ? block access to flash memory programmable decode pld for flexible address mapping of all memories within 8032 space. high-speed clock standard 8032 core (12-cycle) i 2 c interface for peripheral connections analog-to-digital converter (adc) six i/o ports with up to 37 i/o pins 3000 gate pld with 16 macrocells supervisor functions with watchdog timer in-system programming (isp) via jtag zero-power technology single supply voltage ? 4.5 to 5.5v figure 1. 52-lead, thin, quad, flat package tqfp52 (t)
psd3251f 2/128 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 psd3251f device product matrix (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 tqfp52 connections (figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 52-pin package pin description (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 memory map and address space (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8032 mcu registers (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration of ba 16-bit registers (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 stack pointer (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 psw (program status word) register (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 interrupt location of program memory (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 xram-psd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ram address (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 direct addressing (figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 indirect addressing (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 indexed addressing (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 arithmetic instructions (table 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 logical instructions (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 data transfer instructions that access internal data memory space (table 6.) . . . . . . . . . . . . . . 21 shifting a bcd number two digits to the right (using direct movs: 14 bytes) (table 7.) . . . . . . . 22 shifting a bcd number two digits to the right (using direct xchs: 9 bytes) (table 8.) . . . . . . . . 22 shifting a bcd number one digit to the right (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 data transfer instruction that access external data memory space (table 10.) . . . . . . . . . . . . . . 23 lookup table read instruction (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3/128 psd3251f boolean instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 boolean instructions (table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 unconditional jump instructions (table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 machine cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 conditional jump instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 state sequence in psd3251f device (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 psd3251f hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 psd3251f device functional modules (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mcu module discription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sfr memory map (table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 list of all sfr (table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 psd module register address offset (table 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 interrupt system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 external int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 timer 0 and 1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 timer 2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 i2c interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 external int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 usart interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 interrupt system (figure 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 interrupt priority structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 interrupts enable structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 priority levels (table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 sfr register (table 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 description of the ie bits. (table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 description of the iea bits (table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 description of the ip bits (table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 description of the ipa bits (table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 how interrupts are handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 vector addresses (table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 psd3251f 4/128 power-saving mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power-saving mode power consumption (table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 pin status during idle and power-down mode (table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 description of the pcon bits (table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 i/o ports (mcu module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 i/o port functions (table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 p1sfs (91h) (table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 p3sfs (93h) (table 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port type and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 port type and description (part 1) (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 port type and description (part 2) (figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 oscillator (figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 supervisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 reset configuration (figure 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 low vdd voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 watchdog timer overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 watchdog timer key register (wdkey: 0aeh) (table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 description of the wdkey bits (table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 watchdog timer clear register (wdrst: 0a6h) (table 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 description of the wdrst bits (table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 reset pulse width (figure 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 timer/counters (timer 0, timer 1 and timer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 timer 0 and timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 control register (tcon) (table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 description of the tcon bits (table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 tmod register (tmod) (table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 description of the tmod bits (table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 timer/counter mode 0: 13-bit counter (figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5/128 psd3251f timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 timer/counter mode 2: 8-bit auto-reload (figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 timer/counter 2 control register (t2con) (table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 timer/counter 2 operating modes (table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 description of the t2con bits (table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 timer 2 in capture mode (figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 timer 2 in auto-reload mode (figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 timer/counter mode 3: two 8-bit counters (figure 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 standard serial interface (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 multiprocessor communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 serial port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 serial port mode 0, block diagram (figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 serial port control register (scon) (table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 description of the scon bits (table 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 timer 1-generated commonly used baud rates (table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 serial port mode 0, waveforms (figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 serial port mode 1, block diagram (figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 serial port mode 1, waveforms (figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 serial port mode 2, block diagram (figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 serial port mode 2, waveforms (figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 serial port mode 3, block diagram (figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 serial port mode 3, waveforms (figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 analog-to-digital convertor (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 adc interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 a/d block diagram (figure 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 adc sfr memory map (table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 description of the acon bits (table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 adc clock input (table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 block diagram of the i2c bus serial i/o (figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 serial control register (s2con) (table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 description of the s2con bits (table 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 selection of the serial clock frequency scl in master mode (table 50.) . . . . . . . . . . . . . . . . . . . 67 serial status register (s2sta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 data shift register (s2dat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 serial status register (s2sta) (table 51.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 description of the s2sta bits (table 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 data shift register (s2dat) (table 53.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 psd3251f 6/128 address register (s2adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 address register (s2adr) (table 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 start /stop hold time detection register (s2setup) (table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . 69 system cock of 40mhz (table 56.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 system clock setup examples (table 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 psd module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 psd module block diagram (figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 methods of programming different functional blocks of the psd module (table 58.) . . . . . . . . . . 72 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 psdsoft express development tool (figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 psd module register description and address offset . . . . . . . . . . . . . . . . . . . . . . . . 74 register address offset (table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 psd module detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 memory blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 primary flash memory and secondary flash memory description . . . . . . . . . . . . . . . . . . . . . 75 memory block select signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 instructions (table 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 power-down instruction and power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 status bit (table 61.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 data polling flowchart (figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 data toggle flowchart (figure 38.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 specific features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 sector protection/security bit definition ? flash protection register (table 62.) . . . . . . . . . . . . . . 83 sector protection/security bit definition ? secondary flash protection register (table 63.) . . . . . 83 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7/128 psd3251f sector select and sram select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 priority level of memory and i/o components in the psd module (figure 39.) . . . . . . . . . . . . . . . 84 vm register (table 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 separate space mode (figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 combined space mode (figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 page register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 page register (figure 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 dpld and cpld inputs (table 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 the turbo bit in psd module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 pld diagram (figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 decode pld (dpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 dpld logic array (figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 macrocell and i/o port (figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 output macrocell port and data bit assignments (table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 product term allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 cpld output macrocell (figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 input macrocell (figure 47.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 i/o ports (psd module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 general port architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 general i/o port architecture (figure 48.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mcu i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 pld i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 address out mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 jtag in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 port operating modes (table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 port operating mode settings (table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 i/o port latched address output assignments (table 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 port configuration registers (pcr) (table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 port pin direction control, output enable p.t. not defined (table 71.) . . . . . . . . . . . . . . . . . . . . . 98 port pin direction control, output enable p.t. defined (table 72.) . . . . . . . . . . . . . . . . . . . . . . . . 98 port direction assignment example (table 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 psd3251f 8/128 port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 drive register pin assignment (table 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 port b ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 port b structure (figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 port c ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 port c structure (figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 port d ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 port d structure (figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 external chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 port d external chip select signals (figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 apd unit (figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 enable power-down flow chart (figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 power-down mode?s effect on ports (table 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 pld power management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 power management mode registers pmmr0 (table 77.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 power management mode registers pmmr2 (table 78.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 apd counter operation (table 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 i/o pin, register and pld status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 reset (reset) timing (figure 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 status during power-on reset, warm reset and power-down mode (table 80.). . . . . . . . . . 108 programming in-circuit using the jtag serial interface . . . . . . . . . . . . . . . . . . . . . 109 standard jtag signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 jtag port signals (table 81.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 jtag extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 security and flash memory protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 pld icc /frequency consumption (5v range) (figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 psd module example, typ. power calculation at v cc = 5.0v (turbo mode off) (table 82.) . . . 111 9/128 psd3251f maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 absolute maximum ratings (table 83.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 operating conditions (5v device) (table 84.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ac symbols for timing (table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 switching waveforms ? key (figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 dc characteristics (5v device) (table 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 external clock drive (with the 5v mcu module) (table 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 a/d analog specification (table 88.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 input to output disable / enable (figure 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 cpld combinatorial timing (5v device) (table 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 synchronous clock mode timing ? pld (figure 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 cpld macrocell synchronous clock mode timing (5v device) (table 90.). . . . . . . . . . . . . . . . . 118 asynchronous reset / preset (figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 asynchronous clock mode timing (product term clock) (figure 61.) . . . . . . . . . . . . . . . . . . . . . . 119 cpld macrocell asynchronous clock mode timing (5v device) (table 91.) . . . . . . . . . . . . . . . . 119 input macrocell timing (product term clock) (figure 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 input macrocell timing (5v device) (table 92.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 program, write and erase times (5v device) (table 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 reset (reset) timing (5v device) (table 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 v stbyon definitions timing (5v device) (table 95.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 isc timing (figure 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 isc timing (5v device) (table 96.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 mcu module ac measurement i/o waveform (figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 psd module ac float i/o waveform (figure 66.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 external clock cycle (figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 recommended oscillator circuits (figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 psd module ac measurement i/o waveform (figure 69.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 psd module ac measurement load circuit (figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 capacitance (table 97.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 psd3251f 10/128 summary description dual bank flash memories ? concurrent operation, read from memory while erasing and writing the other. in-appli- cation programming (iap) for remote updates ? large 64kbyte main flash memory for appli- cation code, operating systems, or bit maps for graphic user interfaces ? large 16kbyte secondary flash memory di- vided in small sectors. eliminate external ee- prom with software eeprom emulation ? secondary flash memory is large enough for sophisticated communication protocol during iap while continuing critical system tasks large sram with battery back-up option ? 2kbyte sram for rtos, high-level languag- es, communication buffers, and stacks programmable decode pld for flexible address mapping of all memories ? place individual flash and sram sectors on any address boundary ? built-in page register breaks restrictive 8032 limit of 64kbyte address space ? special register swaps flash memory seg- ments between 8032 ?program? space and ?data? space for efficient in-application pro- gramming high-speed clock standard 8032 core (12-cycle) ? 40mhz operation at 5v ? 2 uarts with independent baud rate, three 16-bit timer/counters and two external inter- rupts i 2 c interface for peripheral connections ? capable of master or slave operation 4-channel, 8-bit analog-to-digital converter (adc) with analog supply voltage (v ref ) six i/o ports with up to 37 i/o pins ? multifunction i/o: gpio, i 2 c, pld i/o, super- visor, and jtag ? eliminates need for external latches and logic 3000 gate pld with 16 macrocells ? create glue logic, state machines, delays, etc. ? eliminate external pals, plds, and 74hcxx ? simple psdsoft express software... free supervisor functions ? generates reset upon low voltage or watch- dog time-out. eliminate external supervisor device ? reset input pin; reset output via pld in-system programming (isp) via jtag ? program entire chip in 10 - 25 seconds with no involvement of 8032 ? allows efficient manufacturing, easy product testing, and just-in-time inventory ? eliminate sockets and pre-programmed parts ? program with flashlink tm cable and any pc content security ? programmable security bit blocks access of device programmers and readers zero-power technology ? memories and pld automatically reach standby current between input changes packages ? 52-pin tqfp 11/128 psd3251f table 1. psd3251f device product matrix figure 2. tqfp52 connections note: 1. pull-up resistor of 7.5k ? required on pin 5. 2. nc = not connected. part no. main flash (bit) sec. flash (bit) sram (bit) macro- cells i/o pins timer/ ctr uart ch. i 2 c adc ch. v cc mhz pins UPSD3251f-40t6 512k 128k 16k 16 37 3 2 1 4 5v 40 52 39 p1.5 / adc1 38 p1.4 / adc0 37 p1.3 / txd1 36 p1.2 / rxd1 35 p1.1 / t2x 34 p1.0 / t2 33 v cc 32 xtal2 31 xtal1 30 p3.7 / scl1 29 p3.6 / sda1 28 p3.5 / t1 27 p3.4 / t0 pd1 pc7 pc6 pc5 see note (1) pc4 nc v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 vref gnd reset pb6 pb7 p1.7/adc3 p1.6/adc2 14 15 16 17 18 19 20 21 22 23 24 25 26 p4.7 p4.6 p4.5 p4.4 p4.3 gnd p4.2 p4.1 p4.0 p3.0 / rxd p3.1 / txd p3.2 / exint0 p3.3 / exint1 ai07839 psd3251f 12/128 table 2. 52-pin package pin description port pin signal name pin no. in/out function basic alternate p1.0 t2 34 i/o general i/o port pin timer 2 count input p1.1 t2ex 35 i/o general i/o port pin timer 2 trigger input p1.2 rxd2 36 i/o general i/o port pin 2nd uart receive p1.3 txd2 37 i/o general i/o port pin 2nd uart transmit p1.4 adc0 38 i/o general i/o port pin adc channel 0 input p1.5 adc1 39 i/o general i/o port pin adc channel 1 input p1.6 adc2 40 i/o general i/o port pin adc channel 2 input p1.7 adc3 41 i/o general i/o port pin adc channel 3 input p3.0 rxd1 23 i/o general i/o port pin uart receive p3.1 txd1 24 i/o general i/o port pin uart transmit p3.2 into 25 i/o general i/o port pin interrupt 0 input / timer 0 gate control p3.3 int1 26 i/o general i/o port pin interrupt 1 input / timer 1 gate control p3.4 t0 27 i/o general i/o port pin counter 0 input p3.5 t1 28 i/o general i/o port pin counter 1 input p3.6 sda1 29 i/o general i/o port pin i 2 c bus serial data i/o p3.7 scl1 30 i/o general i/o port pin i 2 c bus clock i/o p4.0 22 i/o general i/o port pin p4.1 21 i/o general i/o port pin p4.2 20 i/o general i/o port pin p4.3 18 i/o general i/o port pin p4.4 17 i/o general i/o port pin p4.5 16 i/o general i/o port pin p4.6 15 i/o general i/o port pin p4.7 14 i/o general i/o port pin pup 5 i/o pull-up resistor required (7.5k ? ) avref 46 o reference voltage input for adc reset_ 44 i active low reset input xtal1 31 i oscillator input pin for system clock xtal2 32 o oscillator output pin for system clock 13/128 psd3251f pb0 52 i/o general i/o port pin 1. pld macro-cell outputs 2. pld inputs 3. latched address out (a0-a7) pb1 51 i/o general i/o port pin pb2 50 i/o general i/o port pin pb3 49 i/o general i/o port pin pb4 48 i/o general i/o port pin pb5 47 i/o general i/o port pin pb6 43 i/o general i/o port pin pb7 42 i/o general i/o port pin pc0 tms 13 i jtag pin 1. pld macro-cell outputs 2. pld inputs 3. sram stand by voltage input (v stby ) 4. sram battery-on indicator (pc4) 5. jtag pins are dedicated pins pc1 tck 12 i jtag pin pc2 v stby 11 i/o general i/o port pin pc3 tstat 10 i/o general i/o port pin pc4 terr 6 i/o general i/o port pin pc5 tdi 4 i jtag pin pc6 tdo 3 o jtag pin pc7 2 i/o general i/o port pin pd1 clkin 1 i/o general i/o port pin 1. pld i/o 2. clock input to pld and apd v cc 8 v cc 33 gnd 9 gnd 19 gnd 45 nc 7 port pin signal name pin no. in/out function basic alternate psd3251f 14/128 architecture overview memory organization the psd3251f device ? s standard 8032 core has separate 64kb address spaces for program mem- ory and data memory. program memory is where the 8032 executes instructions from. data memory is used to hold data variables. flash memory can be mapped in either program or data space. the flash memory consists of two flash memory blocks: the main flash (512kbit) and the second- ary flash (128kbit). except during flash memory programming or update, flash memory can only be read, not written to. a page register is used to access memory beyond the 64k bytes address space. refer to the psd module for details on mapping of the flash memory. the 8032 core has two types of data memory (in- ternal and external) that can be read and written. the internal sram consists of 256 bytes, and in- cludes the stack area. the sfr (special function registers) occupies the upper 128 bytes of the internal sram, the reg- isters can be accessed by direct addressing only. another 2k bytes resides in the psd module that can be mapped to any address space defined by the user. figure 3. memory map and address space ai07425 secondary flash flash main 16kb 64kb ff 7f 0 2kb int. ram ext. ram addressing indirect indirect direct or addressing addressing direct sfr internal ram space (256 bytes) external ram space (movx) flash memory space 15/128 psd3251f registers the 8032 has several registers; these are the pro- gram counter (pc), accumulator (a), b register (b), the stack pointer (sp), the program status word (psw), general purpose registers (r0 to r7), and dptr (data pointer register). accumulator. the accumulator is the 8-bit gen- eral purpose register, used for data operation such as transfer, temporary saving, and conditional tests. the accumulator can be used as a 16-bit register with b register as shown in figure 4. b register. the b register is the 8-bit general purpose register, used for an arithmetic operation such as multiply, division with the accumulator (see figure 5). stack pointer. the stack pointer register is 8 bits wide. it is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the stack pointer is initialized to 07h after reset. this causes the stack to begin at location 08h (see fig- ure 6). program counter. the program counter is a 16- bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pch:00h, pcl:00h). program status word. the program status word (psw) contains several bits that reflect the current state of the cpu and select internal ram (00h to 1fh: bank0 to bank3). the psw is de- scribed in figure 7, page 16. it contains the carry flag, the auxiliary carry flag, the half carry (for bcd operation), the general purpose flag, the register bank select flags, the overflow flag, and parity flag. [carry flag, cy]. this flag stores any carry or not borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruc- tion or rotate instruction. [auxiliary carry flag, ac]. after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. [register bank select flags, rs0, rs1]. this flags select one of four bank(00~07h:bank0, 08~0fh:bank1, 10~17h:bank2, 17~1fh:bank3) in internal ram. [overflow flag, ov]. this flag is set to '1' when an overflow occurs as the result of an arithmetic oper- ation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127 (7fh) or -128 (80h). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [parity flag, p]. this flag reflects on number of ac- cumulator ? s ? 1. ? if the number of accumulator ? s 1 is odd, p=0. otherwise, p=1. the sum of adding accumulator ? s 1 to p is always even. r0~r7. general purpose 8-bit registers that are locked in the lower portion of internal data area. data pointer register. data pointer register is 16-bit wide which consists of two-8bit registers, dph and dpl. this register is used as a data pointer for the data transmission with external data memory in the psd module. figure 4. 8032 mcu registers figure 5. configuration of ba 16-bit registers figure 6. stack pointer ai06636 accumulator b register stack pointer program counter program status word general purpose register (bank0-3) data pointer register pch dptr(dph) a b sp pcl psw r0-r7 dptr(dpl) ai06637 two 8-bit registers can be used as a "ba" 16-bit registers a b a b ai06638 sp (stack pointer) could be in 00h-ffh sp 00h stack area (30h-ffh) 00h-ffh hardware fixed bit 15 bit 0 bit 8 bit 7 psd3251f 16/128 figure 7. psw (program status word) register program memory the program memory consists of two flash mem- ory: 64kbyte main flash and 16kbyte of second- ary flash. the flash memory can be mapped to any address space as defined by the user in the psdsoft tool. it can also be mapped to data memory space during flash memory update or programming. after reset, the cpu begins execution from loca- tion 0000h. as shown in figure 8, each interrupt is assigned a fixed location in program memory. the interrupt causes the cpu to jump to that location, where it commences execution of the service rou- tine. external interrupt 0, for example, is assigned to location 0003h. if external interrupt 0 is going to be used, its service routine must begin at location 0003h. if the interrupt is not going to be used, its service location is available as general purpose program memory. the interrupt service locations are spaced at 8- byte intervals: 0003h for external interrupt 0, 000bh for timer 0, 0013h for external interrupt 1, 001bh for timer 1 and so forth. if an interrupt ser- vice routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval (see figure 8). longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. data memory the internal data memory is divided into four phys- ically separated blocks: 256 bytes of internal ram, 128 bytes of special function registers (sfrs) areas and 2k bytes (xram-psd) in the psd mod- ule. ram four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, con- tain 128 directly addressable bit locations. the stack depth is only limited by the available internal ram space of 256 bytes. xram-psd the 2k bytes of xram-psd resides in the psd module and can be mapped to any address space through the dpld (decoding pld) as defined by the user in psdsoft development tool. the xram- psd has a battery backup feature that allow the data to be retained in the event of a power lost. the battery is connected to the port c pc2 pin. this pin must be configured in psdsoft to be bat- tery back-up. figure 8. interrupt location of program memory ai06639 cy reset value 00h parity flag bit not assigned overflow flag register bank select flags (to select bank0-3) carry flag auxillary carry flag general purpose flag ac fo rs1 rs0 ov p msb lsb psw ai06640 0000h reset 8 bytes interrupt location 0003h 000bh 0013h 008bh 17/128 psd3251f sfr the sfrs can only be addressed directly in the address range from 80h to ffh. table 15, page 29 gives an overview of the special function regis- ters. sixteen address in the sfrs space are both- byte and bit-addressable. the bit-addressable sfrs are those whose address ends in 0h and 8h. the bit addresses in this area are 80h to ffh. table 3. ram address addressing modes the addressing modes in the psd3251f device instruction set are as follows direct addressing indirect addressing register addressing register-specific addressing immediate constants addressing indexed addressing (1) direct addressing. in a direct addressing the operand is specified by an 8-bit address field in the instruction. only internal data ram and sfrs (80~ffh ram) can be directly addressed. example: mov a, 3eh ;a <----- ram[3e] figure 9. direct addressing (2) indirect addressing. in indirect addressing the instruction specifies a register which contains the address of the operand. both internal and ex- ternal ram can be indirectly addressed. the ad- dress register for 8-bit addresses can be r0 or r1 of the selected register bank, or the stack pointer. the address register for 16-bit addresses can only be the 16-bit ? data pointer ? register, dptr. example: mov @r1, #40 h ;[r1] <-----40h figure 10. indirect addressing byte address (in hexadecimal) byte address (in decimal) ffh 255 30h 48 msb bit address (hex) lsb 2fh 7f 7e 7d 7c 7b 7a 79 78 47 2eh777675747372717046 2dh 6f 6e 6d 6c 6b 6a 69 68 45 2ch676665646362616044 2bh 5f 5e 5d 5c 5b 5a 59 58 43 2ah575655545352515042 29h 4f 4e 4d 4c 4b 4a 49 48 41 28h 47 46 45 44 43 42 41 40 40 27h 3f 3e 3d 3c 3b 3a 39 38 39 26h 37 36 35 34 33 32 31 30 38 25h 2f 2e 2d 2c 2b 2a 29 28 37 24h 27 26 25 24 23 22 21 20 36 23h 1f 1e 1d 1c 1b 1a 19 18 35 22h 17 16 15 14 13 12 11 10 34 21h 0f 0e 0d 0c 0b 0a 09 08 33 20h 07 06 05 04 03 02 01 00 32 1fh register bank 3 31 18h 24 17h register bank 2 23 10h 16 0fh register bank 1 15 08h 8 07h register bank 0 7 00h 0 ai06641 3eh program memory 04 a ai06642 r1 55h program memory 55 40h psd3251f 18/128 (3) register addressing. the register banks, containing registers r0 through r7, can be ac- cessed by certain instructions which carry a 3-bit register specification within the opcode of the in- struction. instructions that access the registers this way are code efficient, since this mode elimi- nates an address byte. when the instruction is ex- ecuted, one of four banks is selected at execution time by the two bank select bits in the psw. example: mov psw, #0001000b ; select bank0 mov a, #30h mov r1, a (4) register-specific addressing. some in- structions are specific to a certain register. for ex- ample, some instructions always operate on the accumulator, or data pointer, etc., so no address byte is needed to point it. the opcode itself does that. (5) immediate constants addressing. the val- ue of a constant can follow the opcode in program memory. example: mov a, #10h. (6) indexed addressing. only program memory can be accessed with indexed addressing, and it can only be read. this addressing mode is intend- ed for reading look-up tables in program memory. a 16-bit base register (either dptr or pc) points to the base of the table, and the accumulator is set up with the table entry number. the address of the table entry in program memory is formed by add- ing the accumulator data to the base pointer (see figure 11). example: movc a, @a+dptr figure 11. indexed addressing arithmetic instructions the arithmetic instructions is listed in table 4, page 19. the table indicates the addressing modes that can be used with each instruction to access the 19/128 psd3251f table 4. arithmetic instructions logical instructions table 5, page 20 shows list of the psd3251f de- vice ? s logical instructions. the instructions that perform boolean operations (and, or, exclusive or, not) on bytes perform the operation on a bit- by-bit basis. that is, if the accumulator contains 00110101b and byte contains 01010011b, then: anl a, psd3251f 20/128 table 5. logical instructions mnemonic operation addressing modes dir. ind. reg. imm anl a, 21/128 psd3251f data transfers internal ram. table 6 shows the menu of in- structions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. the mov psd3251f 22/128 first, pointers r1 and r0 are set up to point to the two bytes containing the last four bcd digits. then a loop is executed which leaves the last byte, loca- tion 2eh, holding the last two digits of the shifted number. the pointers are decremented, and the loop is repeated for location 2dh. the cjne in- struction (compare and jump if not equal) is a loop control that will be described later. the loop executed from loop to cjne for r1 = 2eh, 2dh, 2ch, and 2bh. at that point the digit that was orig- inally shifted out on the right has propagated to lo- cation 2ah. since that location should be left with 0s, the lost digit is moved to the accumulator. table 7. shifting a bcd number two digits to the right (using direct movs: 14 bytes) table 8. shifting a bcd number two digits to the right (using direct xchs: 9 bytes) table 9. shifting a bcd number one digit to the right 2a 2b 2c 2d 2e acc mov a,2eh 00 12 34 56 78 78 mov 2eh,2dh 00 12 34 56 56 78 mov 2dh,2ch 00 12 34 34 56 78 mov 2ch,2bh 00 12 12 34 56 78 mov2bh,#0 0000123456 78 2a 2b 2c 2d 2e acc clr a 00 12 34 56 78 00 xch a,2bh 00 00 34 56 78 12 xch a,2ch 00 00 12 56 78 34 xch a,2dh 00 00 12 34 78 56 xch a,2eh 00 00 12 34 56 78 2a 2b 2c 2d 2e acc mov r1,#2eh 00 12 34 56 78 xx mov r0,#2dh 00 12 34 56 78 xx ; loop for r1 = 2eh loop: mov a,@r1 00 12 34 56 78 78 xchd a,@r0 0012345878 76 swap a 00 12 34 58 78 67 mov @r1,a 00 12 34 58 67 67 dec r1 0012345867 67 dec r0 0012345867 67 cnje r1,#2ah,loop 00 12 34 58 67 67 ; loop for r1 = 2dh 00 12 38 45 67 45 ; loop for r1 = 2ch 00 18 23 45 67 23 ; loop for r1 = 2bh 08 01 23 45 67 01 clr a 08 01 23 45 67 00 xch a,2ah 00 01 23 45 67 08 23/128 psd3251f external ram. table 10 shows a list of the data transfer instructions that access external data memory. only indirect addressing can be used. the choice is whether to use a one-byte address, @ri, where ri can be either r0 or r1 of the se- lected register bank, or a two-byte address, @dtpr. note: in all external data ram accesses, the ac- cumulator is always either the destination or source of the data. lookup tables. table 11 shows the two instruc- tions that are available for reading lookup tables in program memory. since these instructions access only program memory, the lookup tables can only be read, not updated. the mnemonic is movc for ? move constant. ? the first movc instruction in table 11 can accommo- date a table of up to 256 entries numbered 0 through 255. the number of the desired entry is loaded into the accumulator, and the data pointer is set up to point to the beginning of the table. then: movc a, @a+dptr copies the desired table entry into the accumula- tor. the other movc instruction works the same way, except the program counter (pc) is used as the table base, and the table is accessed through a subroutine. first the number of the desired en-try is loaded into the accumulator, and the subroutine is called: mov a , entry number call table the subroutine ? table ? would look like this: table: movc a , @a+pc ret the table itself immediately follows the ret (re- turn) instruction is program memory. this type of table can have up to 255 entries, numbered 1 through 255. number 0 cannot be used, because at the time the movc instruction is executed, the pc contains the address of the ret instruction. an entry numbered 0 would be the ret opcode it- self. table 10. data transfer instruction that access external data memory space table 11. lookup table read instruction address width mnemonic operation 8 bits movx a,@ri read external ram @ri 8 bits movx @ri,a write external ram @ri 16 bits movx a,@dptr read external ram @dptr 16 bits movx @dptr,a write external ram @dptr mnemonic operation movc a,@a+dptr read program memory at (a+dptr) movc a,@a+pc read program memory at (a+pc) psd3251f 24/128 boolean instructions the psd3251f device contains a complete boolean (single-bit) processor. one page of the in- ternal ram contains 128 addressable bits, and the sfr space can support up to 128 addressable bits as well. all of the port lines are bit-addressable, and each one can be treated as a separate single- bit port. the instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, or and and instructions. these kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software. the instruction set for the boolean processor is shown in table 12. all bits accesses are by direct addressing. bit addresses 00h through 7fh are in the lower 128, and bit addresses 80h through ffh are in sfr space. note how easily an internal flag can be moved to a port pin: mov c,flag mov p1.0,c in this example, flag is the name of any addres- sable bit in the lower 128 or sfr space. an i/o line (the lsb of port 1, in this case) is set or cleared depending on whether the flag bit is '1' or '0.' the carry bit in the psw is used as the single-bit accumulator of the boolean processor. bit instruc- tions that refer to the carry bit as c assemble as carry-specific instructions (clr c, etc.). the car- ry bit also has a direct address, since it resides in the psw register, which is bit-addressable. note: the boolean instruction set includes anl and orl operations, but not the xrl (exclusive or) operation. an xrl operation is simple to im- plement in software. suppose, for example, it is re- quired to form the exclusive or of two bits: c = bit 1 .xrl. bit2 the software to do that could be as follows: mov c , bit1 jnb bit2, over cpl c over: (continue) first, bit 1 is moved to the carry. if bit2 = 0, then c now contains the correct result. that is, bit 1 .xrl. bit2 = bit1 if bit2 = 0. on the other hand, if bit2 = 1, c now contains the complement of the correct result. it need only be inverted (cpl c) to complete the operation. this code uses the jnb instruction, one of a series of bit-test instructions which execute a jump if the addressed bit is set (jc, jb, jbc) or if the ad- dressed bit is not set (jnc, jnb). in the above case, bit 2 is being tested, and if bit2 = 0, the cpl c instruction is jumped over. jbc executes the jump if the addressed bit is set, and also clears the bit. thus a flag can be tested and cleared in one operation. all the psw bits are directly addressable, so the parity bit, or the gen- eral-purpose flags, for example, are also available to the bit-test instructions. relative offset the destination address for these jumps is speci- fied to the assembler by a label or by an actual ad- dress in program memory. how-ever, the destination address assembles to a relative offset byte. this is a signed (two ? s complement) offset byte which is added to the pc in two ? s complement arithmetic if the jump is executed. the range of the jump is therefore -128 to +127 program memory bytes relative to the first byte fol- lowing the instruction. table 12. boolean instructions mnemonic operation anl c, bit c = a .and. bit anl c, /bit c = c .and. .not. bit orl c, bit c = a .or. bit orl c, /bit c = c .or. .not. bit mov c, bit c = bit mov bit,c bit = c clr c c = 0 clr bit bit = 0 setb c c = 1 setb bit bit = 1 cpl c c = .not. c cpl bit bit = .not. bit jc rel jump if c =1 jnc rel jump if c = 0 jb bit,rel jump if bit =1 jnb bit,rel jump if bit = 0 jbc bit,rel jump if bit = 1; clr bit 25/128 psd3251f jump instructions table 13 shows the list of unconditional jump in- structions. the table lists a single ? jmp add ? in- struction, but in fact there are three sjmp, ljmp, and ajmp, which differ in the format of the desti- nation address. jmp is a generic mnemonic which can be used if the programmer does not care which way the jump is en-coded. the sjmp instruction encodes the destination ad- dress as a relative offset, as described above. the instruction is 2 bytes long, consisting of the op- code and the relative offset byte. the jump dis- tance is limited to a range of -128 to +127 bytes relative to the instruction following the sjmp. the ljmp instruction encodes the destination ad- dress as a 16-bit constant. the instruction is 3 bytes long, consisting of the opcode and two ad- dress bytes. the destination address can be any- where in the 64k program memory space. the ajmp instruction encodes the destination ad- dress as an 11-bit constant. the instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by an- other byte containing the low 8 bits of the destina- tion address. when the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the pc. the high 5 bits stay the same. hence the destination has to be within the same 2k block as the instruction following the ajmp. in all cases the programmer specifies the destina- tion address to the assembler in the same way: as a label or as a 16-bit constant. the assembler will put the destination address into the correct format for the given instruction. if the format required by the instruction will not support the distance to the specified destination address, a ? destination out of range ? message is written into the list file. the jmp @a+dptr instruction supports case jumps. the destination address is computed at ex- ecution time as the sum of the 16-bit dptr regis- ter and the accumulator. typically. dptr is set up with the address of a jump table. in a 5-way branch, for ex-ample, an integer 0 through 4 is loaded into the accumulator. the code to be exe- cuted might be as follows: mov dptr,#jump table mov a,index_number rl a jmp @a+dptr the rl a instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because each entry in the jump table is 2 bytes long: jump table: ajmp case 0 ajmp case 1 ajmp case 2 ajmp case 3 ajmp case 4 table 13 shows a single ? call addr ? instruction, but there are two of them, lcall and acall, which differ in the format in which the subroutine address is given to the cpu. call is a generic mnemonic which can be used if the programmer does not care which way the address is encoded. the lcall instruction uses the 16-bit address for- mat, and the subroutine can be anywhere in the 64k program memory space. the acall instruc- tion uses the 11-bit format, and the subroutine must be in the same 2k block as the instruction fol- lowing the acall. in any case, the programmer specifies the subrou- tine address to the assembler in the same way: as a label or as a 16-bit constant. the assembler will put the address into the correct format for the giv- en instructions. subroutines should end with a ret instruction, which returns execution to the instruction following the call. reti is used to return from an interrupt service routine. the only difference between ret and reti is that reti tells the interrupt control system that the interrupt in progress is done. if there is no interrupt in progress at the time reti is executed, then the reti is functionally identical to ret. table 13. unconditional jump instructions mnemonic operation jmp addr jump to addr jmp @a+dptr jump to a+dptr call addr call subroutine at addr ret return from subroutine reti return from interrupt nop no operation psd3251f 26/128 table 14 shows the list of conditional jumps avail- able to the psd3251f device user. all of these jumps specify the destination address by the rela- tive offset method, and so are limited to a jump dis- tance of -128 to +127 bytes from the instruction following the conditional jump instruction. impor- tant to note, however, the user specifies to the as- sembler the actual destination address the same way as the other jumps: as a label or a 16-bit con- stant. there is no zero bit in the psw. the jz and jnz instructions test the accumulator data for that con- dition. the djnz instruction (decrement and jump if not zero) is for loop control. to execute a loop n times, load a counter byte with n and terminate the loop with a djnz to the beginning of the loop, as shown below for n = 10: mov counter,#10 loop: (begin loop) (end loop) djnz counter, loop (continue) the cjne instruction (compare and jump if not equal) can also be used for loop control as in ta- ble 9. two bytes are specified in the operand field of the instruction. the jump is executed only if the two bytes are not equal. in the example of table 9 shifting a bcd number one digits to the right, the two bytes were data in r1 and the constant 2ah. the initial data in r1 was 2eh. every time the loop was executed, r1 was decre- mented, and the looping was to continue until the r1 data reached 2ah. another application of this instruction is in ? greater than, less than ? comparisons. the two bytes in the operand field are taken as unsigned integers. if the first is less than the second, then the carry bit is set (1). if the first is greater than or equal to the second, then the carry bit is cleared. machine cycles a machine cycle consists of a sequence of six states, numbered s1 through s6. each state time lasts for two oscillator periods. thus, a machine cycle takes 12 oscillator periods or 1s if the oscil- lator frequency is 12mhz. refer to figure 12, page 27. each state is divided into a phase 1 half and a phase 2 half. state sequence in psd3251f de- vice shows that retrieve/execute sequences in states and phases for various kinds of instructions. normally two program retrievals are generated during each machine cycle, even if the instruction being executed does not require it. if the instruc- tion being executed does not need more code bytes, the cpu simply ignores the extra retrieval, and the program counter is not incremented. execution of a one-cycle instruction (figure 12, page 27) begins during state 1 of the machine cy- cle, when the opcode is latched into the instruction register. a second retrieve occurs during s4 of the same machine cycle. execution is complete at the end of state 6 of this machine cycle. the movx instructions take two machine cycles to execute. no program retrieval is generated dur- ing the second cycle of a movx instruction. this is the only time program retrievals are skipped. the retrieve/execute sequence for movx instruc- tion is shown in figure 12, page 27 (d). table 14. conditional jump instructions mnemonic operation addressing modes dir. ind. reg. imm jz rel jump if a = 0 accumulator only jnz rel jump if a 0 accumulator only djnz 27/128 psd3251f figure 12. state sequence in psd3251f device osc. (xtal2) read opcode read next opcode read next opcode and discard read next opcode and discard read 2nd byte no fetch no fetch no ale s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 read opcode read next opcode s1 s2 s3 s4 s5 s6 read opcode read next opcode s1 s2 s3 s4 s5 s6 read next opcode and discard s1 s2 s3 s4 s5 s6 read next opcode and discard read next opcode and discard read opcode (movx) read next opcode s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 addr data access external memory ai06822 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 a. 1-byte, 1-cycle instruction, e.g. inc a b. 2-byte, 1-cycle instruction, e.g. add a, adrs c. 1-byte, 2-cycle instruction, e.g. inc dptr d. 1-byte, 2-cycle movx instruction psd3251f 28/128 psd3251f hardware description the psd3251f device has a modular architec- ture with two main functional modules: the mcu module and the psd module. the mcu module consists of a standard 8032 core, peripherals and other system supporting functions. the psd mod- ule provides configurable program and data mem- ories to the 8032 cpu core. in addition, it has its own set of i/o ports and a pld with 16 macrocells for general logic implementation. ports b, c, and d are general purpose programmable i/o ports that have a port architecture which is different from ports in the mcu module. the psd module communicates with the cpu core through the internal address, data bus (a0- a15, d0-d7) and control signals (rd_, wr_, psen_ , ale, reset_). the user defines the de- coding pld in the psdsoft development tool and can map the resources in the psd module to any program or data address space. figure 13. psd3251f device functional modules ai07861 4 channel adc 512kb main flash decode pld 16kb sram cpld - 16 macrocells jtag isp port 1 port 3 2 uarts interrupt 3 timer / counters 256 byte sram 8032 core port 3, uart, intr, timers,i 2 c psd internal bus 8032 internal bus port 1, timers and 2nd uart and adc port 4 port b, pld i/o, and gpio port d gpio port c, jtag, pld i/o, and gpio vcc, gnd, xtal 128kb secondary flash dedicated pins i2c reset logic lvd & wdt bus interface reset d0-d7 a0-a15 rd,psen wr,ale page register psd module mcu module 29/128 psd3251f mcu module discription this section provides a detail description of the mcu module system functions and peripherals, including: special function registers timers/counter interrupts supervisory function (lvd and watchdog) usart power saving modes i 2 c bus on-chip oscillator adc i/o ports special function registers a map of the on-chip memory area called the spe- cial function register (sfr) space is shown in ta- ble 15. note: in the sfrs not all of the addresses are oc- cupied. unoccupied addresses are not implement- ed on the chip. read accesses to these addresses will in general return random data, and write accesses will have no effect. user soft- ware should write '0s' to these unimplemented lo- cations. table 15. sfr memory map note: 1. register can be bit addressing f8 ff f0 b (1) f7 e8 ef e0 acc (1) e7 d8 s2con s2sta s2dat s2adr df d0 psw (1) d7 c8 t2con (1) t2mod rcap2l rcap2h tl2 th2 cf c0 p4 (1) c7 b8 ip (1) bf b0 p3 (1) pscl0l pscl0h pscl1l pscl1h ipa b7 a8 ie (1) wdkey af a0 wdrst iea a7 98 scon sbuf scon2 sbuf2 9f 90 p1 (1) p1sfs p3sfs ascl adat acon 97 88 tcon (1) tmod tl0 tl1 th0 th1 8f 80 sp dpl dph pcon 87 psd3251f 30/128 table 16. list of all sfr sfr addr reg name bit register name reset value comments 76543210 80 81 sp 07 stack ptr 82 dpl 00 data ptr low 83 dph 00 data ptr high 87 pcon smod smod1 lvren adsfint rclk1 tclk1 pd idle 00 power ctrl 88 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 timer / cntr control 89 tmod gate c/t m1 m0 gate c/t m1 m0 00 timer / cntr mode control 8a tl0 00 timer 0 low 8b tl1 00 timer 1 low 8c th0 00 timer 0 high 8d th1 00 timer 1 high 90 p1 ff port 1 91 p1sfs p1s7 p1s6 p1s5 p1s4 00 port 1 select register 93 p3sfs p3s7 p3s6 00 port 3 select register 94 95 ascl 00 8-bit prescaler for adc clock 96 adat adat7 adat6 adat5 adat4 adat3 adat2 adat1 adat0 00 adc data register 97 acon aden ads1 ads0 adst adsf 00 adc control register 98 scon sm0 sm1 sm2 ren tb8 rb8 ti ri 00 serial control register 99 sbuf 00 serial buffer 9a scon2 sm0 sm1 sm2 ren tb8 rb8 ti ri 00 2nd uart ctrl register 9b sbuf2 00 2nd uart serial buffer a0 a1 a2 a3 a4 a5 31/128 psd3251f a6 wdrst 00 watch dog reset a7 iea es2 ei 2 c 00 interrupt enable (2nd) a8 ie ea - et2 es et1 ex1 et0 ex0 00 interrupt enable a9 aa ab ae wdkey 00 watch dog key register b0 p3 ff port 3 b1 pscl0l 00 prescaler 0 low (8-bit) b2 pscl0h 00 prescaler 0 high (8-bit) b3 pscl1l 00 prescaler 1 low (8-bit) b4 pscl1h 00 prescaler 1 high (8-bit) b7 ipa ps2 pi2c 00 interrupt priority (2nd) b8 ip pt2 ps pt1 px1 pt0 px0 00 interrupt priority c0 p4 ff new port 4 c8 t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00 timer 2 control c9 t2mod dcen 00 timer 2 mode ca rcap2l 00 timer 2 reload low cb rcap2h 00 timer 2 reload high cc tl2 00 timer 2 low byte cd th2 00 timer 2 high byte d0 psw cy ac fo rs1 rs0 ov p 00 program status word d1 d2 s2setup 00 i 2 c (s2) setup d4 sfr addr reg name bit register name reset value comments 76543210 psd3251f 32/128 d5 d6 d7 d8 d9 da db dc s2con cr2 en1 sta sto addr aa cr1 cr0 00 i 2 c bus control reg dd s2sta gc stop intr tx-md bbusy blost ack_r slv 00 i 2 c bus status de s2dat 00 data hold register df s2adr 00 i 2 c address e0 acc 00 accumulator f0 b 00 b register sfr addr reg name bit register name reset value comments 76543210 33/128 psd3251f table 17. psd module register address offset csiop addr offset register name bit register name reset value comments 76543210 01 data in (port b) 03 control (port b) 00 05 data out (port b) 00 07 direction (port b) 00 09 drive (port b) 00 0b input macrocell (port b) 0d enable out (port b) 10 data in (port c) 12 data out (port c) 00 14 direction (port c) 00 16 drive (port c) 00 18 input macrocell (port c) 1a enable out (port c) 11 data in (port d) * * * * * * only bit 1 is used 13 data out (port d) * * * * * * 00 only bit 1 is used 15 direction (port d) * * * * * * 00 only bit 1 is used 17 drive (port d) * * * * * * 00 only bit 1 is used 1b enable out (port d) ***** * only bit 1 is used 20 output macrocells ab 21 output macrocells bc 22 mask macrocells ab 23 mask macrocells bc c0 primary flash protection sec3_ prot sec2_ prot sec1_ prot sec0_ prot bit = 1 sector is protected c2 secondary flash protection security _bit ***** sec1_ prot sec0_ prot security bit = 1 device is secured psd3251f 34/128 note: (register address = csiop address + address offset; where csiop address is defined by user in psdsoft) * indicates bit is not used and need to set to '0.' b0 pmmr0 * * pld mcells clk pld array- clk pld turbo * apd enable *00 control pld power consumption b4 pmmr2 * pld array ale pld array cntl2 pld array cntl1 pld array cntl0 **00 blocking inputs to pld array e0 page 00 page register e2 vm periph- mode ** fl_ data boot_ data fl_ code boot_ code sr_ code configure 8032 program and data space csiop addr offset register name bit register name reset value comments 76543210 35/128 psd3251f interrupt system there are interrupt requests from 10 sources as follows (see figure 14, page 36). int0 external interrupt 2nd usart interrupt timer 0 interrupt i 2 c interrupt int1 external interrupt (or adc interrupt) timer 1 interrupt usart interrupt timer 2 interrupt external int0 ? the int0 can be either level-active or transition- active depending on bit it0 in register tcon. the flag that actually generates this interrupt is bit ie0 in tcon. ? when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. ? if the interrupt was level activated then the inter- rupt request flag remains set until the requested interrupt is actually generated. then it has to de- activate the request before the interrupt service routine is completed, or else another interrupt will be generated. timer 0 and 1 interrupts ? timer 0 and timer 1 interrupts are generated by tf0 and tf1 which are set by an overflow of their respective timer/counter registers (except for timer 0 in mode 3). ? these flags are cleared by the internal hard- ware when the interrupt is serviced. timer 2 interrupt ? timer 2 interrupt is generated by tf2 which is set by an overflow of timer 2. this flag has to be cleared by the software - not by hardware. ? it is also generated by the t2ex signal (timer 2 external interrupt p1.1) which is controlled by exen2 and exf2 bits in the t2con register. i 2 c interrupt ? the interrupt of the i 2 c is generated by bit intr in the register s2sta. ? this flag is cleared by hardware. external int1 ? the int1 can be either level active or transition active depending on bit it1 in register tcon. the flag that actually generates this interrupt is bit ie1 in tcon. ? when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. ? if the interrupt was level activated then the inter- rupt request flag remains set until the requested interrupt is actually generated. then it has to de- activate the request before the interrupt service routine is completed, or else another interrupt will be generated. ? the adc can take over the external int1 to generate an interrupt on conversion being com- pleted psd3251f 36/128 figure 14. interrupt system ai07427 int0 usart timer 0 i2c int1 timer 1 2nd usart timer 2 high low interrupt polling interrupt sources ie / ip / ipa priority global enable 37/128 psd3251f usart interrupt ? the usart interrupt is generated by ri (re- ceive interrupt) or ti (transmit interrupt). ? when the usart interrupt is generated, the corresponding request flag must be cleared by the software. the interrupt service routine will have to check the various usart registers to determine the source and clear the correspond- ing flag. ? both usart ? s are identical, except for the addi- tional interrupt controls in the bit 4 of the addi- tional interrupt control registers (a7h, b7h). interrupt priority structure each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority special function register ip and ipa. 0 = low priority 1 = high priority a low priority interrupt may be interrupted by a high priority interrupt level interrupt. a high priority interrupt routine cannot be interrupted by any oth- er interrupt source. if two interrupts of different pri- ority occur simultaneously, the high priority level request is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling se- quence. interrupts enable structure each interrupt source can be individually enabled or disabled by setting or clearing a bit in the inter- rupt enable special function register ie and iea. all interrupt source can also be globally disabled by the clearing bit ea in ie (see table 19). please see tables 20, 21, 22, and 23 for individual bit de- scriptions. table 18. priority levels table 19. sfr register source priority with level int0 0 (highest) 2nd usart 1 timer 0 2 i 2 c3 int1 4 reserved 5 timer 1 6 reserved 7 1st usart 8 timer 2+exf2 9 (lowest) sfr addr reg name bit register name reset value comments 76543210 a7 iea ??? es2 ?? ei 2 c ? 00 interrupt enable (2nd) a8 ie ea ? et2 es et1 ex1 et0 ex0 00 interrupt enable b7 ipa ??? ps2 ?? pi 2 c ? 00 interrupt priority (2nd) b8 ip ?? pt2 ps pt1 px1 pt0 px0 00 interrupt priority psd3251f 38/128 table 20. description of the ie bits. table 21. description of the iea bits table 22. description of the ip bits bit symbol function 7ea disable all interrupts: 0: no interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit 6 ? reserved 5 et2 enable timer 2 interrupt 4 es enable usart interrupt 3 et1 enable timer 1 interrupt 2 ex1 enable external interrupt (int1) 1 et0 enable timer 0 interrupt 0 ex0 enable external interrupt (int0) bit symbol function 7 ? not used 6 ? not used 5 ? not used 4 es2 enable 2nd usart interrupt 3 ? not used 2 ? not used 1 ei2c enable i 2 c interrupt 0 ? not used bit symbol function 7 ? reserved 6 ? reserved 5 pt2 timer 2 interrupt priority level 4 ps usart interrupt priority level 3 pt1 timer 1 interrupt priority level 2 px1 external interrupt (int1) priority level 1 pt0 timer 0 interrupt priority level 0 px0 external interrupt (int0) priority level 39/128 psd3251f table 23. description of the ipa bits how interrupts are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during fol- lowing machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle w ill find it and the interrupt system will generate an lcall to the appropriate service rou- tine, provided this h/w generated lcall is not blocked by any of the following conditions: ? an interrupt of equal priority or higher priority level is already in progress. ? the current machine cycle is not the final cycle in the execution of the instruction in progress. ? the instruction in progress is reti or any ac- cess to the interrupt priority or interrupt enable registers. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cy- cle. note: if an interrupt flag is active but being re- sponded to for one of the above mentioned condi- tions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the inter- rupt flag was once active but not serviced is not re- membered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate service routine. the hardware gener- ated lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that de- pends on the source of the interrupt being vec- tored to as shown in table 24. execution proceeds from that location until the reti instruction is encountered. the reti instruc- tion informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note: a simple ret instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future inter- rupts impossible. table 24. vector addresses bit symbol function 7 ? not used 6 ? not used 5 ? not used 4 ps2 2nd usart interrupt priority level 3 ? not used 2 ? not used 1pi2ci 2 c interrupt priority level 0 ? not used source vector address int0 0003h 2nd usart 004bh timer 0 000bh i 2 c 0043h int1 0013h timer 1 001bh 1st usart 0023h timer 2+exf2 002bh psd3251f 40/128 power-saving mode two software selectable modes of reduced power consumption are implemented (see table 25). idle mode the following functions are switched off. ? cpu (halted) the following function remain active during idle mode. ? external interrupts ? timer 0, timer 1, timer 2 ? usart ? 8-bit adc ? i 2 c interface note: interrupt or reset terminates the idle mode. power-down mode ? system clock halted ? lvd logic remains active ? sram contents remains unchanged ? the sfrs retain their value until a reset is as- serted note: the only way to exit power-down mode is a reset . power control register the idle and power-down modes are activated by software via the pcon register (see tables 26 and table 27, page 41). idle mode the instruction that sets pcon.0 is the last in- struction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. there are three ways to terminate the idle mode. ? activation of any enabled interrupt will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and follow- ing return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic '1' to pcon.0. ? external hardware reset: the hardware reset is required to be active for two machine cycle to complete the reset operation. ? internal reset: the microcontroller restarts after 3 machine cycles in all cases. power-down mode the instruction that sets pcon.1 is the last exe- cuted prior to going into the power-down mode. once in power-down mode, the oscillator is stopped. the contents of the on-chip ram and the special function register are preserved. the power-down mode can be terminated by an external reset. table 25. power-saving mode power consumption table 26. pin status during idle and power-down mode mode addr/data ports1,3,4 i 2 c idle maintain data maintain data active power-down maintain data maintain data disable sfr addr reg name bit register name reset value comments 76543210 87 pcon smod smod1 lvren adsfint rclk1 tclk1 pd idle 00 power ctrl 41/128 psd3251f table 27. description of the pcon bits note: 1. see the t2con register for details of the flag description i/o ports (mcu module) the mcu module has three ports: port1, port3, and port 4. (refer to the psd module section on i/ o ports b, c and d). port1 - port3 are the same as in the standard 8032 micro-controllers, with the exception of the addi- tional special peripheral functions (see table 28). all ports are bi-directional. pins of which the alter- native function is not used may be used as normal bi-directional i/o. the use of port1- port4 pins as alternative func- tions are carried out automatically by the psd3251f device provided the associated sfr bit is set high. table 28. i/o port functions bit symbol function 7 smod double baud data rate bit uart 6 smod1 double baud data rate bit 2nd uart 5 lvren lvr disable bit (active high) 4 adsfint enable adc interrupt 3 rclk1 (1) received clock flag (uart 2) 2 tclk1 (1) transmit clock flag (uart 2) 1 pd activate power-down mode (high enable) 0 idl activate idle mode (high enable) port name main function alternate port 1 gpio timer 2 - bits 0,1 2nd uart - bits 2,3 adc - bits 4..7 port 3 gpio uart - bits 0,1 interrupt - bits 2,3 timers - bits 4,5 i 2 c - bits 6,7 port 4 gpio psd3251f 42/128 the following sfr registers (tables 29 and 30) are used to control the mapping of alternate func- tions onto the i/o port bits. port 1 alternate func- tions are controlled using the p1sfs register, except for timer 2 and the 2nd uart which are enabled by their configuration registers. p1.0 to p1.3 are default to gpio after reset. port 3 pins 6 and 7 have been modified from the standard 8032. these pins that were used for read and write control signals are now gpio or i 2 c bus pins. the read and write pins are assigned to dedicated pins. port 3 (i 2 c) alternate functions are controlled us- ing the p3sfs special function selection regis- ter. after a reset, the i/o pins default to gpio. the alternate function is enabled if the corresponding bit in the p3sfs register is set to '1.' other port 3 alternative functions (uart, interrupt, and timer/ counter) are enabled by their configuration regis- ter and do not require setting of the bits in p3sfs. table 29. p1sfs (91h) table 30. p3sfs (93h) 76543210 0=port 1.7 1=ach3 0=port 1.6 1=ach2 0=port 1.5 1=ach1 0=port 1.4 1=ach0 bits reserved bits reserved 76543210 0 = port 3.7 1 = scl from i 2 c unit 0 = port 3.6 1 = sda from i 2 c unit bits are reserved. 43/128 psd3251f port type and description figure 15. port type and description (part 1) ai07862 symbol circuit description in / out reset i schmitt input with internal pull-up cmos compatible interface nfc : 400ns wr, rd,ale, psen o output only xtal1, xtal2 i o on-chip oscillator on-chip feedback resistor stop in the power down mode external clock input available cmos compatible interface nfc xon psd3251f 44/128 figure 16. port type and description (part 2) oscillator the oscillator circuit of the psd3251f device is a single stage inverting amplifier in a pierce oscilla- tor configuration (see figure 17). the circuitry be- tween xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ce- ramic resonator can be used as the feedback ele- ment to complete the oscillator circuit. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output. to drive the psd3251f device ex- ternally, xtal1 is driven from an external source and xtal2 left open-circuit. figure 17. oscillator ai07863 symbol circuit function in/ out port1 <3:0>, port3, port4<7:3,1:0> i/o port4.2 bidirectional i/o port with internal pull-ups schmitt input cmos compatible interface bidirectional i/o port with internal pull-ups schmitt input. ttl compatible interface port1 < 7:4 > i/o bidirectional i/o port with internal pull-ups schmitt input cmos compatible interface analog input option i/o an_enb ai06620 xtal1 xtal2 8 to 40 mhz xtal1 xtal2 external clock 45/128 psd3251f supervisory there are three ways to invoke a reset and initial- ize the psd3251f device: via the external reset pin via the internal lvr block. via watch dog timer the reset mechanism is illustrated in figure 18. each reset source will cause an internal reset signal active. the cpu responds by executing an internal reset and puts the internal registers in a defined state. this internal reset is also routed as an active low reset input to the psd module. external reset the reset pin is connected to a schmitt trigger for noise reduction. a reset is accomplished by holding the reset pin low for at least 1ms at power up while the oscillator is running. refer to ac spec on other reset timing requirements. low v dd voltage reset an internal reset is generated by the lvr circuit when the v dd drops below the reset threshold. af- ter v dd reaching back up to the reset threshold, the reset signal will remain asserted for 10ms before it is released. on initial power-up the lvr is enabled (default). after power-up the lvr can be disabled via the lvren bit in the pcon reg- ister. note: the lvr logic is still functional in both the idle and power-down modes. the reset threshold: 5v operation: 4v +/- 0.25v this logic supports approximately 0.1v of hystere- sis and 1s noise-cancelling delay. watchdog timer overflow the watchdog timer generates an internal reset when its 22-bit counter overflows. see watch- dog timer, page 46 for details. figure 18. reset configuration ai07429 reset cpu & peri. noise cancel lvr s q r cpu clock sync 10ms timer wdt psd_rst "active low" 10ms at 40mhz 50ms at 8mhz psd3251f 46/128 watchdog timer the hardware watchdog timer (wdt) resets the psd3251f device when it overflows. the wdt is intended as a recovery method in situations where the cpu may be subjected to a software upset. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware/software malfunction, the soft- ware will fail to reload the timer. this failure will re- sult in a reset upon overflow thus preventing the processor running out of control. in the idle mode the watchdog timer and reset cir- cuitry remain active. the wdt consists of a 22-bit counter, the watchdog timer reset (wdrst) sfr and watchdog key register (wdkey). since the wdt is automatically enabled while the processor is running. the user only needs to be concerned with servicing it. the 22-bit counter overflows when it reaches 4194304 (3fffffh). the wdt increments once every machine cycle. this means the user must reset the wdt at least every 4194304 machine cycles (1.258 seconds at 40mhz). to reset the wdt the user must write a value between 00-7eh to the wdrst register. the value that is written to the wdrst is loaded to the 7msb of the 22-bit counter. this allows the user to pre-loaded the counter to an initial value to generate a flexible watchdog time out period. writing a ? 00 ? to wdrst clears the counter. the watchdog timer is controlled by the watchdog key register, wdkey. only pattern 01010101 (=55h), disables the watchdog timer. the rest of pattern combinations will keep the watchdog timer enabled. this security key will prevent the watch- dog timer from being terminated abnormally when the function of the watchdog timer is needed. in idle mode, the oscillator continues to run. to prevent the wdt from resetting the processor while in idle, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. watchdog reset pulse width depends on the clock frequency (see figure 19, page 47). the reset pe- riod is tf osc x 12 x 2 22 . the reset pulse width is tf osc x 12 x 2 15 . table 31. watchdog timer key register (wdkey: 0aeh) table 32. description of the wdkey bits table 33. watchdog timer clear register (wdrst: 0a6h) table 34. description of the wdrst bits note: the watchdog timer (wdt) is enabled at power-up or reset and must be served or disabled. 76543210 wdkey7 wdkey6 wdkey5 wdkey4 wdkey3 wdkey2 wdkey1 wdkey0 bit symbol function 7 to 0 wdkey7 to wdkey0 enable or disable watchdog timer. 01010101 (=55h): disable watchdog timer. others: enable watchdog timer 76543210 reserved wdrst6 wdrst5 wdrst4 wdrst3 wdrst2 wdrst1 wdrst0 bit symbol function 7 ? reserved 6 to 0 wdrst6 to wdrst0 to reset watchdog timer, write any value beteen 00h and 7eh to this register. this value is loaded to the 7 most significant bits of the 22-bit counter. for example: mov wdrst,#1eh 47/128 psd3251f figure 19. reset pulse width timer/counters (timer 0, timer 1 and timer 2) the psd3251f device has three 16-bit timer/ counter registers: timer 0, timer 1 and timer 2. all of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. in the ? timer ? function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 6 cpu clock periods, the count rate is 1/6 of the cpu clock frequency or 1/12 of oscilla- tor frequency (f osc ). in the ? counter ? function, the register is increment- ed in response to a 1-to-0 transition at its corre- sponding external input pin, t0 or t1. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cy- cle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was de- tected. since it takes 2 machine cycles (24 f osc clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the f osc . there are no restrictions on the duty cycle of the external in- put signal, but to ensure that a given level is sam- pled at least once before it changes, it should be held for at least one full cycle. in addition to the ? timer ? or ? counter ? selection, timer 0 and timer 1 have four operating modes from which to select. timer 0 and timer 1 the ? timer ? or ? counter ? function is selected by control bits c/t in the special function register tmod. these timer/counters have four operat- ing modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for timers/ counters. mode 3 is different. the four op- erating modes are de-scribed in the following text. table 35. control register (tcon) reset period (1.258 second at 40mhz) (about 6.291 seconds at 8mhz) reset pulse width (about 10ms at 40mhz, about 50ms at 8mhz) ai06823 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 psd3251f 48/128 table 36. description of the tcon bits table 37. tmod register (tmod) table 38. description of the tmod bits bit symbol function 7tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on or off 5tf0 timer 0 overflow flag. set by hardier on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on or off 3ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed 2it1 interrupt 1 type control bit. set/cleared by software to specify falling-edge/low-level triggered external interrupt 1ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed 0it0 interrupt 0 type control bit. set/cleared by software to specify falling-edge/low-level triggered external interrupt 76543210 gate c/t m1 m0 gate c/t m1 m0 bit symbol timer function 7gate timer 1 gating control when set. timer/counter 1 is enabled only while int1 pin is high and tr1 control pin is set. when cleared, timer 1 is enabled whenever tr1 control bit is set 6c/t timer or counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from t1 input pin) 5 m1 (m1,m0)=(0,0): 13-bit timer/counter, th1, with tl1 as 5-bit prescaler (m1,m0)=(0,1): 16-bit timer/counter. th1 and tl1 are cascaded. there is no prescaler. (m1,m0)=(1,0): 8-bit auto-reload timer/counter. th1 holds a value which is to be reloaded into tl1 each time it overflows (m1,m0)=(1,1): timer/counter 1 stopped 4m0 3gate timer 0 gating control when set. timer/counter 0 is enabled only while int0 pin is high and tr0 control pin is set. when cleared, timer 0 is enabled whenever tr0 control bit is set 2c/t timer or counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from t0 input pin) 1 m1 (m1,m0)=(0,0): 13-bit timer/counter, th0, with tl0 as 5-bit prescaler (m1,m0)=(0,1): 16-bit timer/counter. th0 and tl0 are cascaded. there is no prescaler. (m1,m0)=(1,0): 8-bit auto-reload timer/counter. th0 holds a value which is to be reloaded into tl0 each time it overflows (m1,m0)=(1,1): tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits 0m0 49/128 psd3251f mode 0. putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 20 shows the mode 0 operation as it applies to timer 1. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all '1s' to all '0s,' it sets the timer interrupt flag tf1. the counted input is enabled to the timer when tr1 = 1 and either gate = 0 or /int1 = 1. (setting gate = 1 allows the timer to be controlled by external in- put /int1, to facilitate pulse width measurements). tr1 is a control bit in the special function regis- ter tcon (tcon control register). gate is in tmod. the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl1. the upper 3 bits of tl1 are indeterminate and should be ignored. setting the run flag does not clear the registers. mode 0 operation is the same for the timer 0 as for timer 1. substitute tr0, tf0, and /int0 for the corresponding timer 1 signals in figure 20. there are two different gate bits, one for timer 1 and one for timer 0. mode 1. mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. figure 20. timer/counter mode 0: 13-bit counter ai06622 f osc tf1 interrupt gate tr1 int1 pin t1 pin control tl1 (5 bits) th1 (8 bits) c/t = 0 c/t = 1 12 psd3251f 50/128 mode 2. mode 2 configures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in figure 21. overflow from tl1 not only sets tf1, but also reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 2 operation is the same for timer/counter 0. timer 2 like timer 0 and 1, timer 2 can operate as either an event timer or as an event counter. this is se- lected by bit c/t2 in the special function register t2con (see table 39). it has three operating modes: capture, auto-reload, and baud rate generator (see table 40, page 51), which are se- lected by bits in the t2con as shown in table 41, page 51. in the capture mode there are two op- tions which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter which upon overflowing sets bit tf2, the timer 2 overflow bit, which can be used to gener- ate an interrupt. if exen2 = 1, t hen timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt. the cap- ture mode is illustrated in figure 22, page 52. in the auto-reload mode, there are again two op- tions, which are selected by bit exen2 in t2con. if exen2 = 0, t hen when timer 2 rolls over it not only sets tf2 but also causes the timer 2 regis- ters to be reloaded with the 16-bit value in regis- ters rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2. the auto-reload mode is illustrated in standard serial interface (uart) figure 23, page 52. the baud rate gen- eration mode is selected by (rclk, rclk1) = 1 and/or (tclk, tclk1) = 1. it will be described in conjunction with the serial port. figure 21. timer/counter mode 2: 8-bit auto-reload table 39. timer/counter 2 control register (t2con) 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t 2cp/rl 2 ai06623 f osc tf1 interrupt gate tr1 int1 pin t1 pin control tl1 (8 bits) th1 (8 bits) c/t = 0 c/t = 1 12 51/128 psd3251f table 40. timer/counter 2 operating modes note: = falling edge table 41. description of the t2con bits note: 1. the rclk1 and tclk1 bits in the pcon register control uart 2, and have the same function as rclk and tclk. mode t2con t2mod decn t2con exen p1.1 t2ex remarks input clock rxclk or txclk cp/ rl 2 tr2 internal external (p1.0/t2) 16-bit auto- reload 0 0 1 0 0 x reload upon overflow f osc /12 max f osc /24 0010 1 reload trigger (falling edge) 0 0 1 1 x 0 down counting 0 0 1 1 x 1 up counting 16-bit capture 011x 0x 16-bit timer/counter (only up counting) f osc /12 max f osc /24 011x 1 capture (th1,tl2) (rcap2h,rcap2l) baud rate generator 1x1x 0x no overflow interrupt request (tf2) f osc /12 max f osc /24 1x1x 1 extra external interrupt (timer 2) off x x 0 x x x timer 2 stops ?? bit symbol function 7tf2 timer 2 overflow flag. set by a timer 2 overflow, and must be cleared by software. tf2 will not be set when either (rclk, rclk1)=1 or (tclk, tclk)=1 6exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2=1. when timer 2 interrupt is enabled, exf2=1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software 5 rclk (1) receive clock flag (uart 1). when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. tclk=0 causes timer 1 overflow to be used for the receive clock 4 tclk (1) transmit clock flag (uart 1). when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk=0 causes timer 1 overflow to be used for the transmit clock 3 exen2 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2=0 causes time 2 to ignore events at t2ex 2 tr2 start/stop control for timer 2. a logic 1 starts the timer 1c/t 2 timer or counter select for timer 2. cleared for timer operation (input from internal system clock, t cpu ); set for external event counter operation (negative edge triggered) 0cp/rl 2 capture/reload flag. when set, capture will occur on negative transition of t2ex if exen2=1. when cleared, auto-reload will occur either with timer 2 overflows, or negative transitions of t2ex when exen2=1. when either (rclk, rclk1)=1 or (tclk, tclk)=1, this bit is ignored, and timer is forced to auto-reload on timer 2 overflow psd3251f 52/128 figure 22. timer 2 in capture mode figure 23. timer 2 in auto-reload mode ai06625 f osc tf2 capture tr2 t2 pin control tl2 (8 bits) th2 (8 bits) c/t2 = 0 c/t2 = 1 12 exp2 control exen2 rcap2l rcap2h t2ex pin timer 2 interrupt transition detector ai06626 f osc tf2 reload tr2 t2 pin control tl2 (8 bits) th2 (8 bits) c/t2 = 0 c/t2 = 1 12 exp2 control exen2 rcap2l rcap2h t2ex pin timer 2 interrupt transition detector 53/128 psd3251f mode 3. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 24. tl0 uses the timer 0 con- trol bits: c/t, gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cy- cles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the ? timer 1 ? in- terrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an psd3251f device can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. figure 24. timer/counter mode 3: two 8-bit counters ai06624 f osc tf0 interrupt gate tr0 int0 pin t0 pin control tl0 (8 bits) c/t = 0 c/t = 1 12 f osc tf1 interrupt control th1 (8 bits) 12 tr1 psd3251f 54/128 standard serial interface (uart) the psd3251f device provides two standard 8032 uart serial ports. the first port is connected to pin p3.0 (rx) and p3.1 (tx). the second port is connected to pin p1.2 (rx) and p1.3(tx). the op- eration of the two serial ports are the same and are controlled by the scon and scon2 registers. the serial port is full duplex, meaning it can trans- mit and receive simultaneously. it is also receive- buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf (or sbuf2 for the second serial port). writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0. serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are trans- mitted/received (lsb first). the baud rate is fixed at 1/12 the f osc . mode 1. 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2. 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of '0' or '1.' or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is pro- grammable to either 1/32 or 1/64 the oscillator fre- quency. mode 3. 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination regis- ter. reception is initiated in mode 0 by the condi- tion ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multi- processor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be pro- grammed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multi-proces- sor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is '1' in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupt- ed by a data byte. an ad-dress byte, however, will interrupt all slaves, so that each slave can exam- ine the received byte and see if it is being ad- dressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren ? t being ad- dressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive inter- rupt will not be activated unless a valid stop bit is received. 55/128 psd3251f serial port control register the serial port control and status register is the special function register scon (scon2 for the second port), shown in figure 25. this register (see tables 42 and 43) contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port in- terrupt bits (ti and ri). figure 25. serial port mode 0, block diagram table 42. serial port control register (scon) 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri ai06824 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift shift clock serial port interrupt s6 ren r1 rx clock start tx clock start shift shift send receive t r cl ds q 7 6 5 4 3 2 1 0 rxd p3.0 alt input function rxd p3.0 alt output function txd p3.1 alt output function psd3251f 56/128 table 43. description of the scon bits bit symbol function 7 sm0 (sm1,sm0)=(0,0): shift register. baud rate = f osc /12 (sm1,sm0)=(1,0): 8-bit uart. baud rate = variable (sm1,sm0)=(0,1): 8-bit uart. baud rate = f osc /64 or f osc /32 (sm1,sm0)=(1,1): 8-bit uart. baud rate = variable 6sm1 5sm2 enables the multiprocessor communication features in mode 2 and 3. in mode 2 or 3, if sm2 is set to '1,' ri will not be activated if its received 8th data bit (rb8) is '0.' in mode 1, if sm2=1, ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be '0' 4ren enables serial reception. set by software to enable reception. clear by software to disable reception 3tb8 the 8th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired 2rb8 in modes 2 and 3, this bit contains the 8th data bit that was received. in mode 1, if sm2=0, rb8 is the snap bit that was received. in mode 0, rb8 is not used 1ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software 0ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit in the other modes, in any serial reception (except for sm2). must be cleared by software 57/128 psd3251f baud rates. the baud rate in mode 0 is fixed: mode 0 baud rate = f osc / 12 the baud rate in mode 2 depends on the value of bit smod = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. mode 2 baud rate = (2 smod / 64) x f osc in the psd3251f device, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. using timer 1 to generate baud rates. when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows (see table 44, page 58): mode 1,3 baud rate = (2 smod / 32) x (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either ? timer ? or ? counter ? operation, and in any of its 3 running modes. in the most typical applica- tions, it is configured for ? timer ? operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1,3 baud rate = (2 smod / 32) x (f osc / (12 x [256 ? (th1)])) one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and con- figuring the timer to run as a 16-bit timer (high nib- ble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 20 lists various commonly used baud rates and how they can be obtained from timer 1. using timer/counter 2 to generate baud rates. in the psd3251f device, timer 2 select- ed as the baud rate generator by setting tclk and/or rclk (see figure 20, page 49 timer/ counter 2 control register (t2con)). note: the baud rate for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer into its baud rate generator mode. the rclk and tclk bits in the t2con register configure uart 1. the rclk1 and tclk1 bits in the pcon register configure uart 2. the baud rate generator mode is similar to the auto-reload mode, in that a roll over in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. now, the baud rates in modes 1 and 3 are deter- mined at timer 2 ? s overflow rate as follows: mode 1,3 baud rate = timer 2 overflow rate / 16 the timer can be configured for either ? timer ? or ? counter ? operation. in the most typical applica- tions, it is configured for ? timer ? operation (c/t2 = 0). ? timer ? operation is a little different for timer 2 when it ? s being used as a baud rate generator. normally, as a timer it would increment every ma- chine cycle (thus at the 1/6 the cpu clock frequen- cy). in the case, the baud rate is given by the formula: mode 1,3 baud rate = f osc / (32 x [65536 - (rcap2h, rcap2l)] where (rcap2h, rcap2l) is the content of rc2h and rc2l taken as a 16-bit unsigned inte- ger. timer 2 also be used as the baud rate generating mode. this mode is valid only if rclk + tclk = 1 in t2con or in pcon. note: a roll-over in th2 does not set tf2, and will not generate an interrupt. therefore, the timer in- terrupt does not have to be disabled when timer 2 is in the baud rate generator mode. note: if exen2 is set, a 1-to-0 transition in t2ex will set exf2 but will not cause a reload from (rcap2h, rcap2l) to (th2, tl2). thus when timer 2 is in use as a baud rate generator, t2ex can be used as an extra external interrupt, if de- sired. it should be noted that when timer 2 is running (tr2 = 1) in ? timer ? function in the baud rate gen- erator mode, one should not try to read or write th2 or tl2. under these conditions the timer is being incremented every state time, and the results of a read or write may not be accu- rate. the rc registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. turn the timer off (clear tr2) before accessing the timer 2 or rc registers, in this case. psd3251f 58/128 table 44. timer 1-generated commonly used baud rates more about mode 0. serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed at 1/12 the f osc . figure 25, page 55 shows a simplified functional diagram of the serial port in mode 0, and associat- ed timing. transmission is initiated by any instruction that uses sbuf as a destination register. the ? write to sbuf ? signal at s6p2 also loads a '1' into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between ? write to sbuf ? and activation of send. send enables the output of the shift register to the alternate out-put function line of rxd and also en- able shift clock to the alternate output func- tion line of txd. shift clock is low during s3, s4, and s5 of every machine cycle, and high dur- ing s6, s1, and s2. at s6p2 of every machine cy- cle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deacti- vate send and set t1. both of these actions occur at s1p1. both of these actions occur at s1p1 of the 10th machine cycle after ? write to sbuf. ? reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enables shift clock to the alternate output function line of txd. shift clock makes transitions at s3p1 and s6p1 of every machine cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the rxd pin at s5p2 of the same machine cycle. as data bits come in from the right, '1s' shift out to the left. when the '0' that was initially loaded into the right-most position arrives at the left-most po- sition in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. baud rate f osc smod timer 1 c/t mode reload value mode 0 max: 1mhz 12mhz x x x x mode 2 max: 375k 12mhz 1 x x x modes 1, 3: 62.5k 12mhz 1 0 2 ffh 19.2k 11.059mhz 1 0 2 fdh 9.6k 11.059mhz 0 0 2 fdh 4.8k 11.059mhz 0 0 2 fah 2.4k 11.059mhz 0 0 2 f4h 1.2k 11.059mhz 0 0 2 e8h 137.5 11.059mhz 0 0 2 1dh 110 6mhz00272h 110 12mhz001feebh 59/128 psd3251f figure 26. serial port mode 0, waveforms more about mode 1. ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first). and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the psd3251f device the baud rate is deter- mined by the timer 1 or timer 2 overflow rate. figure 27, page 60 shows a simplified functional diagram of the serial port in mode 1, and associat- ed timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the ? write to sbuf ? signal also loads a '1' into the 9th bit po- sition of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the di- vide-by-16 counter. (thus, the bit times are syn- chronized to the divide-by-16 counter, not to the ? write to sbuf ? signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left (see figure 28, page 60). when the msb of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after ? write to sbuf. ? reception is initiated by a detected 1-to-0 transi- tion at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been es- tablished. when a transition is detected, the di- vide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an-other 1-to- 0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the re- set of the rest of the frame will proceed. as data bits come in from the right, '1s' shift out to the left. when the start bit arrives at the left-most position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generat- ed: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the re- ceived frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. ai06825 write to sbuf send shift rxd (data out) txd (shift clock) t write to scon ri receive shift rxd (data in) txd (shift clock) s6p2 s3p1 s6p1 clear ri receive transmit d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 psd3251f 60/128 figure 27. serial port mode 1, block diagram figure 28. serial port mode 1, waveforms ai06826 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 timer1 overflow timer2 overflow 0 01 1 01 tclk rclk smod ai06843 write to sbuf data shift txd t1 rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit 61/128 psd3251f more about modes 2 and 3. eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a pro- grammable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of '0' or '1.' on receive, the data bit goes into rb8 in scon. the baud rate is programma- ble to either 1/16 or 1/32 the cpu clock frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1. figure 29, page 62 and figure 31, page 63 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the ? write to sbuf ? signal also loads tb8 into the 9th bit po- sition of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next roll-over in the divide-by- 16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the ? write to sbuf ? signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that (see figure 30, page 62 and figure 32, page 63). the first shift clocks a '1' (the stop bit) into the 9th bit position of the shift register. there-after, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the out-put position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then de- activate send and set ti. this occurs at the 11th divide-by 16 rollover after ? write to subf. ? reception is initiated by a detected 1-to-0 transi- tion at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been es- tablished. when a transition is detected, the di- vide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an- other 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and recep- tion of the rest of the frame will proceed. as data bits come in from the right, '1s' shift out to the left. when the start bit arrives at the left-most position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following con- ditions are met at the time the final shift pulse is generated: 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1 if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input. psd3251f 62/128 figure 29. serial port mode 2, block diagram figure 30. serial port mode 2, waveforms ai06844 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 phase2 clock 1/2*f osc 01 smod ai06845 write to sbuf data shift txd ti rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit tb8 d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit rb8 stop bit generator 63/128 psd3251f figure 31. serial port mode 3, block diagram figure 32. serial port mode 3, waveforms ai06846 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 timer1 overflow timer2 overflow 0 01 1 01 tclk rclk smod ai06847 write to sbuf data shift txd ti rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit tb8 d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit rb8 stop bit generator psd3251f 64/128 analog-to-digital convertor (adc) the analog to digital (a/d) converter allows con- version of an analog input to a corresponding 8-bit digital value. the a/d module has four analog in- puts, which are multiplexed into one sample and hold. the output of the sample and hold is the in- put into the converter, which generates the result via successive approximation. the analog supply voltage is connected to avref of ladder resis- tance of a/d module. the a/d module has two registers which are the control register acon and a/d result register adat. the register acon, shown in table 45 and table 46, page 65, controls the operation of the a/ d converter module. to use analog inputs, i/o is selected by p1sfs register. also an 8-bit prescal- er ascl divides the main system clock input down to approximately 6mhz clock that is required for the adc logic. appropriate values need to be load- ed into the prescaler based upon the main mcu clock frequency prior to use. the processing of conversion starts when the start bit adst is set to '1.' after one cycle, it is cleared by hardware. the register adat contains the results of the a/d conversion. when conver- sion is completed, the result is loaded into the adat the a/d conversion status bit adsf is set to '1.' the block diagram of the a/d module is shown in figure 33. the a/d status bit adsf is set auto- matically when a/d conversion is completed, cleared when a/d conversion is in process. the ascl should be loaded with a value that re- sults in a clock rate of approximately 6mhz for the adc using the following formula (see table 47, page 65): adc clock input = (f osc / 2) / (prescaler register value +1) where f osc is the mcu clock input frequency the conversion time for the adc can be calculat- ed as follows: adc conversion time = 8 clock * 8bits * (adc clock) ~= 10.67usec (at 6mhz) adc interrupt the adsf bit in the acon register is set to '1' when the a/d conversion is complete. the status bit can be driven by the mcu, or it can be config- ured to generate a falling edge interrupt when the conversion is complete. the adsf interrupt is enabled by setting the ads- fint bit in the pcon register. once the bit is set, the external int1 interrupt is disabled and the adsf interrupt takes over as int1. int1 must be configured as if it is an edge interrupt input. the inp1 pin (p3.3) is available for general i/o func- tions, or timer1 gate control. figure 33. a/d block diagram ai06627 input mux ach0 ach1 ach2 ach3 acon internal bus adat avref ladder resistor d ecode s/h successive approximation circuit conversion complete interrupt 65/128 psd3251f table 45. adc sfr memory map table 46. description of the acon bits table 47. adc clock input sfr addr reg name bit register name reset value comments 76543210 95 ascl 00 8-bit prescaler for adc clock 96 adat adat7 adat6 adat5 adat4 adat3 adat2 adat1 adat0 00 adc data register 97 acon aden ads1 ads0 adst adsf 00 adc control register bit symbol function 7 to 6 ? reserved 5 aden adc enable bit: 0: adc shut off and consumes no operating current 1: enable adc 4 ? reserved 3 to 2 ads1, ads0 analog channel select 0, 0 channel0 (ach0) 0, 1 channel1 (ach1) 1, 0 channel2 (ach2) 1, 1 channel3 (ach3) 1 adst adc start bit: 0: force to zero 1: start an adc; after one cycle, bit is cleared to '0' 0 adsf adc status bit: 0: a/d conversion is in process 1: a/d conversion is completed, not in process mcu clock frequency prescaler register value adc clock 40mhz 2 6.7mhz 36mhz 2 6mhz 24mhz 1 6mhz 12mhz 0 6mhz psd3251f 66/128 i 2 c interface the serial port supports the twin line i 2 c-bus, con- sisting of a data line (sda1), and a clock line (scl1) as shown in figure 34. depending on the configuration, the sda1 and scl1 lines may re- quire pull-up resistors. these lines also function as i/o port lines if the i 2 c bus is not enabled. the system is unique because data transport, clock generation, address recognition, and bus control arbitration are all controlled by hardware. the i 2 c serial i/o has complete autonomy in byte handling and operates in 4 modes. master transmitter master receiver slave transmitter slave receiver these functions are controlled by the sfrs (see tables 48, 49, and table 50, page 67): ? s2con: the control of byte handling and the op- eration of 4 mode. ? s2sta: the contents of its register may also be used as a vector to various service routines. ? s2dat: data shift register. ? s2adr: slave address register. slave address recognition is performed by on-chip h/w. figure 34. block diagram of the i 2 c bus serial i/o ai07430 scl1 sda1 bus clock generator arbitration and sync. logic shift register status register 70 slave address 70 control register 70 70 internal bus 67/128 psd3251f table 48. serial control register (s2con) table 49. description of the s2con bits table 50. selection of the serial clock frequency scl in master mode 76543210 cr2 enii sta sto addr aa cr1 cr0 bit symbol function 7cr2 this bit along with bits cr1and cr0 determines the serial clock frequency when sio is in the master mode. 6enii enable iic. when eni1 = 0, the iic is disabled. sda and scl outputs are in the high impedance state. 5sta start flag. when this bit is set, the sio h/w checks the status of the i 2 c-bus and generates a start condition if the bus free. if the bus is busy, the sio will generate a repeated start condition when this bit is set. 4sto stop flag. with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i 2 c bus, the i 2 c hardware clears the sto flag. note: this bit have to be set before 1 cycle interrupt period of stop. that is, if this bit is set, stop condition in master mode is generated after 1 cycle interrupt period. 3 addr this bit is set when address byte was received. must be cleared by software. 2aa acknowledge enable signal. if this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: own slave address is received a data byte is received while the device is programmed to be a master receiver a data byte is received while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. sio release sda line as high during the acknowledge clock pulse. 1cr1 these two bits along with the cr2 bit determine the serial clock frequency when sio is in the master mode. 0cr0 cr2 cr1 cr0 f osc divisor bit rate (khz) at f osc 12mhz 24mhz 36mhz 40mhz 0 0 0 16 375 750 x x 0 0 1 24 250 500 750 833 0 1 0 30 200 400 600 666 0 1 1 60 100 200 300 333 1 0 0 120 50 100 150 166 1 0 1 240 25 50 75 83 1 1 0 480 12.5 25 37.5 41 1 1 1 960 6.25 12.5 18.75 20 psd3251f 68/128 serial status register (s2sta) s2sta is a ? read-only ? register. the contents of this register may be used as a vector to a service routine. this optimized the response time of the software and consequently that of the i 2 c bus. the status codes for all possible modes of the i 2 c bus interface are given table 52. this flag is set, and an interrupt is generated, after any of the following events occur: 1. own slave address has been received during aa = 1: ack_int 2. the general call address has been received while gc(s2adr.0) = 1 and aa = 1: 3. a data byte has been received or transmitted in master mode (even if arbitration is lost): ack_int 4. a data byte has been received or transmitted as selected slave: ack_int 5. a stop condition is received as selected slave receiver or transmitter: stop_int data shift register (s2dat) s2dat contains the serial data to be transmitted or data which has just been received. the msb (bit 7) is transmitted or received first; that is, data shifted from right to left. table 51. serial status register (s2sta) table 52. description of the s2sta bits note: 1. interrupt flag bit (intr, s2sta bit 5) is cleared by hardware as reading s2sta register. 2. i 2 c interrupt flag (intr) can occur in below case. table 53. data shift register (s2dat) 76543210 gc stop intr tx_mode bbusy blost /ack_rep slv bit symbol function 7 gc general call flag 6 stop stop flag. this bit is set when a stop condition is received 5 intr (1,2) interrupt flag. this bit is set when an i 2 c interrupt condition is requested 4tx_mode transmission mode flag. this bit is set when the i 2 c is a transmitter; otherwise this bit is reset 3 bbusy bus busy flag. this bit is set when the bus is being used by another master; otherwise, this bit is reset 2blost bus lost flag. this bit is set when the master loses the bus contention; otherwise this bit is reset 1 /ack_rep acknowledge response flag. this bit is set when the receiver transmits the not acknowledge signal this bit is reset when the receiver transmits the acknowledge signal 0slv slave mode flag. this bit is set when the i 2 c plays role in the slave mode; otherwise this bit is reset 76543210 s2dat7 s2dat6 s2dat5 s2dat4 s2dat3 s2dat2 s2dat1 s2dat0 69/128 psd3251f address register (s2adr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/transmitter. the start/stop hold time detection and system clock registers (tables 55 and 56) are included in the i 2 c unit to specify the start/stop detection time to work with the large range of mcu frequency val- ues supported. for example, with a system clock of 40mhz. table 54. address register (s2adr) note: sla6 to sla0: own slave address. table 55. start /stop hold time detection register (s2setup) table 56. system cock of 40mhz table 57. system clock setup examples 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 ? address register name reset value note sfr d2h s2setup 00h to control the start/stop hold time detection for the multi-master i 2 c module in slave mode s1setup, s2setup register value number of sample clock (f osc /2 ? > 50ns) required start/ stop hold time note 00h 1ea 50ns when bit 7 (enable bit) = 0, the number of sample clock is 1ea (ignore bit 6 to bit 0) 80h 1ea 50ns 81h 2ea 100ns 82h 3ea 150ns ... ... ... 8bh 12ea 600ns fast mode i 2 c start/stop hold time specification ... ... ... ffh 128ea 6000ns system clock s1setup, s2setup register value number of sample clock required start/stop hold time 40mhz (f osc /2 ? > 50ns) 8bh 12 ea 600ns 30mhz (f osc /2 ? > 66.6ns) 89h 9 ea 600ns 20mhz (f osc /2 ? > 100ns) 86h 6 ea 600ns 8mhz (f osc /2 ? > 250ns) 83h 3 ea 750ns psd3251f 70/128 psd module the psd module provides configurable program and data memories to the 8032 cpu core (mcu). in addition, it has its own set of i/o ports and a pld with 16 macrocells for general logic implementation. ports b, c, and d are general purpose programmable i/o ports that have a port architecture which is different from the i/o ports in the mcu module. the psd module communicates with the mcu module through the internal address, data bus (a0-a15, d0-d7) and control signals (rd , wr , psen , ale, reset ). the user defines the decoding pld in the psdsoft development tool and can map the resources in the psd module to any program or data address space. figure 35 shows the functional blocks in the psd module. functional overview 512kbit flash memory. this is the main flash memory. it is divided into 4 sectors (16kbytes each) that can be accessed with user-specified addresses. secondary 128kbit flash boot memory. it is divided into 2 sectors (8kbytes each) that can be accessed with user-specified addresses. this secondary memory brings the ability to execute code and update the main flash concurrently. 16kbit sram. the sram ? s contents can be protected from a power failure by connecting an external battery. cpld with 16 output micro cells (omcs) and up to 12 input micro cells (imcs). the cpld may be used to efficiently implement a variety of logic functions for internal and external control. examples include state machines, loadable shift registers, and loadable counters. decode pld (dpld) that decodes address for selection of memory blocks in the psd module. configurable i/o ports (port b, c, and d) that can be used for the following functions: ? mcu i/os ? pld i/os ? latched mcu address output ? special function i/os. ? i/o ports may be configured as open drain outputs. built-in jtag compliant serial port allows full- chip, in-system programmability (isp). with it, you can program a blank device or reprogram a device in the factory or the field. internal page register that can be used to expand the 8032 mcu module address space by a factor of 256. internal programmable power management unit (pmu) that supports a low-power mode called power-down mode. the pmu can automatically detect a lack of the 8032 cpu core activity and put the psd module into power-down mode. erase/write cycles: ? flash memory - 100,000 minimum ? pld - 1,000 minimum ? data retention: 15 year minimum (for main flash memory, boot, pld and configuration bits) 71/128 psd3251f figure 35. psd module block diagram bus interface wr_, rd_, psen_, ale, reset_, a0-a15 d0 ? d7 clkin (pd1) clkin clkin pld input bus prog. port port b power mangmt unit 512kbit primary flash memory 8 sectors vstdby pb0 ? pb7 prog. port port c prog. port port d pc0 ? pc7 pd1 address/data/control bus port b & c ext cs to port d 12 input macrocells port b & c 64 64 128kbit secondary non-volatile memory (boot or data) 2 sectors 16kbit battery backup sram runtime control and i/o registers sram select macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pc2 ) page register embedded algorithm sector selects sector selects global config. & security ai07864 8 bus interface 8032 bus psd3251f 72/128 in-system programming (isp) using the jtag signals on port c, the entire psd module device can be programmed or erased without the use of the mcu. the primary flash memory can also be programmed in-system by the mcu executing the programming algorithms out of the secondary memory, or sram. the sec- ondary memory can be programmed the same way by executing out of the primary flash memo- ry. the pld or other psd module configuration blocks can be programmed through the jtag port or a device programmer. table 58 indicates which programming methods can program different func- tional blocks of the psd module. table 58. methods of programming different functional blocks of the psd module functional block jtag programming device programmer iap primary flash memory yes yes yes secondary flash memory yes yes yes pld array (dpld and cpld) yes yes no psd module configuration yes yes no 73/128 psd3251f development system the psd3200 is supported by psdsoft, a win- dows-based software development tool (win- dows-95, windows-98, windows-nt). a psd module design is quickly and easily produced in a point and click environment. the designer does not need to enter hardware description language (hdl) equations, unless desired, to define psd module pin functions and memory map informa- tion. the general design flow is shown in figure 36. psdsoft is available from our web site (the ad- dress is given on the back page of this data sheet) or other distribution channels. psdsoft directly supports a low cost device pro- grammer from st: flashlink (jtag). the pro- grammer may be purchased through your local distributor/representative. the psd3200 is also supported by third party device programmers. see our web site for the current list. figure 36. psdsoft express development tool merge mcu firmware with psd module configuration psd programmer *.obj file flashlink (jtag) a composite object file is created containing mcu firmware and psd configuration c code generation generate c code specific to psd functions user's choice of 8032 compiler/linker *.obj file available for 3rd party programmers mcu firmware hex or s-record format ai07432 define general purpose logic in cpld point and click definition of combin- atorial and registered logic in cpld. access hdl is available if needed define psd pin and node functions point and click definition of psd pin functions, internal nodes, and mcu system memory map choose psd psd3251f 74/128 psd module register description and address offset table 59 shows the offset addresses to the psd module registers relative to the csiop base ad- dress. the csiop space is the 256 bytes of ad- dress that is allocated by the user to the internal psd module registers. table 59 provides brief de- scriptions of the registers in csiop space. the fol- lowing section gives a more detailed description. table 59. register address offset note: 1. other registers that are not part of the i/o ports. register name port b port c port d other 1 description data in 01 10 11 reads port pin as input, mcu i/o input mode control 03 selects mode between mcu i/o or address out data out 05 12 13 stores data for output to port pins, mcu i/o output mode direction 07 14 15 configures port pin as input or output drive select 09 16 17 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0b 18 reads input macrocells enable out 0d 1a 1b reads the status of the output enable to the i/o port driver output macrocells ab 20 read ? reads output of macrocells ab write ? loads macrocell flip-flops output macrocells bc 21 21 read ? reads output of macrocells bc write ? loads macrocell flip-flops mask macrocells ab 22 blocks writing to the output macrocells ab mask macrocells bc 23 23 blocks writing to the output macrocells bc primary flash protection c0 read-only ? primary flash sector protection secondary flash memory protection c2 read-only ? psd module security and secondary flash memory sector protection pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd module memory areas in program and/or data space on an individual basis. 75/128 psd3251f psd module detailed operation as shown in figure 13, the psd module consists of five major types of functional blocks: memory block pld blocks i/o ports power management unit (pmu) jtag interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the psd module has the following memory blocks: primary flash memory secondary flash memory sram the memory select signals for these blocks origi- nate from the decode pld (dpld) and are user- defined in psdsoft express. primary flash memory and secondary flash memory description the primary flash memory is divided into 4 sec- tors (16kbytes each). the secondary flash mem- ory is divided into 2 sectors (8kbytes each). each sector of either memory block can be separately protected from program and erase cycles. flash memory may be erased on a sector-by-sec- tor basis. flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. during a program or erase cycle in flash memory, the status can be output on ready/busy (pc3). this pin is set up using psdsoft express configu- ration. memory block select signals the dpld generates the select signals for all the internal memory blocks (see the section entitled ? plds, ? page 88). each of the eight sectors of the primary flash memory has a select signal (fs0- fs3) which can contain up to three product terms. each of the 2 sectors of the secondary flash memory has a select signal (csboot0- csboot1) which can contain up to three product terms. having three product terms for each select signal allows a given sector to be mapped in pro- gram or data space. ready/busy (pc3). this signal can be used to output the ready/busy status of the flash memo- ry. the output on ready/busy (pc3) is a 0 (busy) when flash memory is being written to, or when flash memory is being erased. the output is a 1 (ready) when no write or erase cycle is in progress. memory operation. the primary flash memory and secondary flash memory are addressed through the mcu bus. the mcu can access these memories in one of two ways: ? the mcu can execute a typical bus write or read operation . ? the mcu can execute a specific flash memory instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash memory to invoke an embedded algo- rithm. these instructions are summarized in ta- ble 60. typically, the mcu can read flash memory using read operations, just as it would read a rom de- vice. however, flash memory can only be altered using specific erase and program instructions. for example, the mcu cannot write a single byte di- rectly to flash memory as it would write a byte to ram. to program a byte into flash memory, the mcu must execute a program instruction, then test the status of the program cycle. this status test is achieved by a read operation or polling ready/busy (pc3). psd3251f 76/128 instructions an instruction consists of a sequence of specific operations. each received byte is sequentially de- coded by the psd module and not executed as a standard write operation. the instruction is exe- cuted when the correct number of bytes are prop- erly received and the time between two consecutive bytes is shorter than the time-out pe- riod. some instructions are structured to include read operations after the initial write opera- tions. the instruction must be followed exactly. any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory resets the device logic into read mode (flash memory is read like a rom device). the flash memory supports the instructions sum- marized in table 60: flash memory: erase memory by chip or sector suspend or resume sector erase program a byte reset to read mode read sector protection status these instructions are detailed in table 60. for ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the sec ond cy- cle. address signals a15-a12 are don ? t care dur- ing the instruction write cycles. however, the appropriate sector select (fs0-fs3 or csboot0-csboot1) must be selected. the primary and secondary flash memories have the same instruction set. the sector select signals determine which flash memory is to receive and execute the instruction. the primary flash memo- ry is selected if any one of sector select (fs0- fs3) is high, and the secondary flash memory is selected if any one of sector select (csboot0- csboot1) is high. 77/128 psd3251f table 60. instructions note: 1. all bus cycles are write bus cycles, except the ones with the ? read ? label 2. all values are in hexadecimal: x = don ? t care. addresses of the form xxxxh, in this table, must be even addresses ra = address of the memory location to be read rd = data read from location ra during the read cycle pa = address of the memory location to be programmed. addresses are latched on the falling edge of write strobe (wr , cntl0). pa is an even address for psd in word programming mode. pd = data word to be programmed at location pa. data is latched on the rising edge of write strobe (wr , cntl0) sa = address of the sector to be erased or verified. the sector select (fs0-fs3 or csboot0-csboot1) of the sector to be erased, or verified, must be active (high). 3. sector select (fs0-fs3 or csboot0-csboot1) signals are active high, and are defined in psdsoft express. 4. only address bits a11-a0 are used in instruction decoding. 5. no unlock or instruction cycles are required when the device is in the read mode 6. the reset instruction is required to return to the read mode after reading the sector protection status, or if the error flag bit (dq5) goes high. 7. additional sectors to be erased must be written at the end of the sector erase instruction within 80s. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. the system may perform read and program cycles in non-erasing sectors, read the sector protection status when in the suspend sector erase mode. the suspend sector erase instruction is valid only during a sector erase cycle. 10. the resume sector erase instruction is valid only during the suspend sector erase mode. 11. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction i s intended. the mcu must retrieve, for example, the code from the secondary flash memory when reading the sector protection status of the primary flash memory. instruction fs0-fs3 or csboot0- csboot1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read (5) 1 ? read ? rd @ ra read sector protection (6,8,11) 1 aah@ x555h 55h@ xaaah 90h@ x555h read status @ xx02h program a flash byte (11) 1 aah@ x555h 55h@ xaaah a0h@ x555h pd@ pa flash sector erase (7,11) 1 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 30h@ sa 30h (7) @ next sa flash bulk erase (11) 1 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 10h@ x555h suspend sector erase (9) 1 b0h@ xxxxh resume sector erase (10) 1 30h@ xxxxh reset (6) 1 f0h@ xxxxh psd3251f 78/128 power-down instruction and power-up mode power-up mode. the psd module internal logic is reset upon power-up to the read mode. sector select (fs0-fs3 and csboot0-csboot1) must be held low, and write strobe (wr , cntl0) high, during power-up for maximum se- curity of the data contents and to remove the pos- sibility of a byte being written on the first edge of write strobe (wr , cntl0). any write cycle initiation is locked when v cc is below v lko . read under typical conditions, the mcu may read the primary flash memory or the secondary flash memory using read operations just as it would a rom or ram device. alternately, the mcu may use read operations to obtain status information about a program or erase cycle that is currently in progress. lastly, the mcu may use instructions to read special data from these memory blocks. the following sections describe these read functions. read memory contents. primary flash memo- ry and secondary flash memory are placed in the read mode after power-up, chip reset, or a reset flash instruction (see table 60, page 77). the mcu can read the memory contents of the pri- mary flash memory or the secondary flash mem- ory by using read operations any time the read operation is not part of an instruction. read memory sector protection status. the primary flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read opera- tion (see table 60). during the read operation, address bits a6, a1, and a0 must be '0,' '1,' and '0,' respectively, while sector select (fs0-fs3 or csboot0-csboot1) designates the flash memory sector whose protection has to be veri- fied. the read operation produces 01h if the flash memory sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (primary flash memory or secondary flash mem- ory) can also be read by the mcu accessing the flash protection registers in psd i/o space. see the section entitled ? flash memory sector pro- tect, ? page 83, for register definitions. reading the erase/program status bits. the flash memory provides several status bits to be used by the mcu to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the mcu spends performing these tasks and are defined in table 61, page 79. the status bits can be read as many times as needed. for flash memory, the mcu can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see the section entitled ? programming flash memory, ? page 80, for de- tails. data polling flag (dq7). when erasing or pro- gramming in flash memory, the data polling flag bit (dq7) outputs the complement of the bit being entered for programming/writing on the dq7 bit. once the program instruction or the write oper- ation is completed, the true logic value is read on the data polling flag bit (dq7) (in a read opera- tion). ? data polling is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). it must be performed at the address being pro- grammed or at an address within the flash memory sector being erased. ? during an erase cycle, the data polling flag bit (dq7) outputs a '0.' after completion of the cy- cle, the data polling flag bit (dq7) outputs the last bit programmed (it is a '1' after erasing). ? if the byte to be programmed is in a protected flash memory sector, the instruction is ignored. ? if all the flash memory sectors to be erased are protected, the data polling flag bit (dq7) is re- set to '0' for about 100s, and then returns to the previous addressed byte. no erasure is per- formed. 79/128 psd3251f toggle flag (dq6). the flash memory offers an- other way for determining when the program cycle is completed. during the internal write operation and when either the fs0-fs3 or csboot0- csboot1 is true, the toggle flag bit (dq6) tog- gles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling stops and the data read on the data bus d0-d7 is the addressed memory byte. the device is now accessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. ? the toggle flag bit (dq6) is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase in- struction). ? if the byte to be programmed belongs to a pro- tected flash memory sector, the instruction is ignored. ? if all the flash memory sectors selected for era- sure are protected, the toggle flag bit (dq6) toggles to '0' for about 100s and then returns to the previous addressed byte. error flag (dq5). during a normal program or erase cycle, the error flag bit (dq5) is to 0. this bit is set to '1' when there is a failure during flash memory byte program, sector erase, or bulk erase cycle. in the case of flash memory programming, the er- ror flag bit (dq5) indicates the attempt to program a flash memory bit from the programmed state, '0,' to the erased state, '1,' which is not valid. the error flag bit (dq5) may also indicate a time-out condition while attempting to program a byte. in case of an error in a flash memory sector erase or byte program cycle, the flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. other flash memory sectors may still be used. the error flag bit (dq5) is reset after a reset flash instruction. erase time-out flag (dq3). the erase time- out flag bit (dq3) reflects the time-out period al- lowed between two consecutive sector erase in- structions. the erase time-out flag bit (dq3) is reset to 0 after a sector erase cycle for a time pe- riod of 100s + 20% unless an additional sector erase instruction is decoded. after this time peri- od, or when the additional sector erase instruction is decoded, the erase time-out flag bit (dq3) is set to '1.' table 61. status bit note: 1. x = not guaranteed value, can be read either '1' or '0.' 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fs0-fs3 and csboot0-csboot1 are active high. functional block fs0-fs3/csboot0- csboot1 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash memory v ih data polling to g g l e flag error flag x erase time- out xxx psd3251f 80/128 programming flash memory flash memory must be erased prior to being pro- grammed. a byte of flash memory is erased to all '1s' (ffh), and is programmed by setting selected bits to '0.' the mcu may erase flash memory all at once or by-sector, but not byte-by-byte. howev- er, the mcu may program flash memory byte-by- byte. the primary and secondary flash memories re- quire the mcu to send an instruction to program a byte or to erase sectors (see table 60). once the mcu issues a flash memory program or erase instruction, it must check for the status bits for completion. the embedded algorithms that are invoked support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or ready/busy (pc3). data polling. polling on the data polling flag bit (dq7) is a method of checking whether a program or erase cycle is in progress or has completed. figure 37 shows the data polling algorithm. when the mcu issues a program instruction, the embedded algorithm begins. the mcu then reads the location of the byte to be programmed in flash memory to check status. the data polling flag bit (dq7) of this location becomes the complement of b7 of the original data byte to be programmed. the mcu continues to poll this location, comparing the data polling flag bit (dq7) and monitoring the er- ror flag bit (dq5). when the data polling flag bit (dq7) matches b7 of the original data, and the er- ror flag bit (dq5) remains '0,' the embedded algo- rithm is complete. if the error flag bit (dq5) is '1,' the mcu should test the data polling flag bit (dq7) again since the data polling flag bit (dq7) may have changed simultaneously with the error flag bit (dq5) (see figure 37). the error flag bit (dq5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the mcu at- tempted to program a '1' to a bit that was not erased (not erased is logic '0'). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the flash memory with the byte that was intended to be written. when using the data polling method during an erase cycle, figure 37 still applies. however, the data polling flag bit (dq7) is '0' until the erase cy- cle is complete. a '1' on the error flag bit (dq5) in- dicates a time-out condition on the erase cycle; a '0' indicates no error. the mcu can read any loca- tion within the sector being erased to get the data polling flag bit (dq7) and the error flag bit (dq5). psdsoft express generates ansi c code func- tions which implement these data polling algo- rithms. figure 37. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no 81/128 psd3251f data toggle. checking the toggle flag bit (dq6) is a method of determining whether a pro- gram or erase cycle is in progress or has complet- ed. figure 38 shows the data toggle algorithm. when the mcu issues a program instruction, the embedded algorithm begins. the mcu then reads the location of the byte to be programmed in flash memory to check status. the toggle flag bit (dq6) of this location toggles each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this loca- tion, checking the toggle flag bit (dq6) and mon- itoring the error flag bit (dq5). when the toggle flag bit (dq6) stops toggling (two consecutive reads yield the same value), and the error flag bit (dq5) remains '0,' the embedded algorithm is complete. if the error flag bit (dq5) is '1,' the mcu should test the toggle flag bit (dq6) again, since the toggle flag bit (dq6) may have changed simultaneously with the error flag bit (dq5) (see figure 38). the error flag bit(dq5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the mcu at- tempted to program a '1' to a bit that was not erased (not erased is logic '0'). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to flash memory with the byte that was intended to be written. when using the data toggle method after an erase cycle, figure 38 st ill applies. the toggle flag bit (dq6) toggles until the erase cycle is complete. a '1' on the error flag bit (dq5) indi- cates a time-out condition on the erase cycle; a '0' indicates no error. the mcu can read any location within the sector being erased to get the toggle flag bit (dq6) and the error flag bit (dq5). psdsoft express generates ansi c code func- tions which implement these data toggling algo- rithms. figure 38. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle psd3251f 82/128 erasing flash memory flash bulk erase. the flash bulk erase instruc- tion uses six write operations followed by a read operation of the status register, as de- scribed in table 60. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading the error flag bit (dq5), the toggle flag bit (dq6), and the data polling flag bit (dq7), as detailed in the section entitled ? pro- gramming flash memory, ? page 80. the error flag bit (dq5) returns a '1' if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the memory with 00h because the psd module automatically does this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory does not accept any instructions. flash sector erase. the sector erase instruc- tion uses six write operations, as described in table 60. additional flash sector erase codes and flash memory sector addresses can be writ- ten subsequently to erase other flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100s. the input of a new sector erase code restarts the time- out period. the status of the internal timer can be monitored through the level of the erase time-out flag bit (dq3). if the erase time-out flag bit (dq3) is '0,' the sector erase instruction has been received and the time-out period is counting. if the erase time-out flag bit (dq3) is '1,' the time-out period has expired and the embedded algorithm is busy erasing the flash memory sector(s). before and during erase time-out, any instruction other than suspend sector erase and resume sector erase instructions abort the cycle that is currently in progress, and reset the device to read mode. during a sector erase, the memory status may be checked by reading the error flag bit (dq5), the toggle flag bit (dq6), and the data polling flag bit (dq7), as detailed in the section entitled ? pro- gramming flash memory, ? page 80. during execution of the erase cycle, the flash memory accepts only reset and suspend sec- tor erase instructions. erasure of one flash mem- ory sector may be suspended, in order to read data from another flash memory sector, and then resumed. suspend sector erase. when a sector erase cycle is in progress, the suspend sector erase in- struction can be used to suspend the cycle by writ- ing 0b0h to any address when an appropriate sector select (fs0-fs3 or csboot0-csboot1) is high. (see table 60). this allows reading of data from another flash memory sector after the erase cycle has been suspended. suspend sec- tor erase is accepted only during an erase cycle and defaults to read mode. a suspend sector erase instruction executed during an erase time- out period, in addition to suspending the erase cy- cle, terminates the time out period. the toggle flag bit (dq6) stops toggling when the internal logic is suspended. the status of this bit must be monitored at an address within the flash memory sector being erased. the toggle flag bit (dq6) stops toggling between 0.1s and 15s af- ter the suspend sector erase instruction has been executed. the flash memory is then automatically set to read mode. if an suspend sector erase instruction was exe- cuted, the following rules apply: ? attempting to read from a flash memory sector that was being erased outputs invalid data. ? reading from a flash sector that was not being erased is valid. ? the flash memory cannot be programmed, and only responds to resume sector erase and reset flash instructions (read is an operation and is allowed). ? if a reset flash instruction is received, data in the flash memory sector that was being erased is invalid. resume sector erase. if a suspend sector erase instruction was previously executed, the erase cycle may be resumed with this instruction. the resume sector erase instruction consists of writing 030h to any address while an appropriate sector select (fs0-fs3 or csboot0-csboot1) is high. (see table 60.) 83/128 psd3251f specific features flash memory sector protect. each primary and secondary flash memory sector can be sepa- rately protected against program and erase cy- cles. sector protection provides additional data security because it disables all program or erase cycles. this mode can be activated through the jtag port or a device programmer. sector protection can be selected for each sector using the psdsoft express configuration pro- gram. this automatically protects selected sectors when the device is programmed through the jtag port or a device programmer. flash memory sec- tors can be unprotected to allow updating of their contents using the jtag port or a device pro- grammer. the mcu can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash memory sector is ignored by the device. the verify operation results in a read of the protected data. this allows a guarantee of the retention of the pro- tection status. the sector protection status can be read by the mcu through the flash memory protection regis- ters (in the csiop block). see table 62 and table 63. reset flash. the reset flash instruction con- sists of one write cycle (see table 60). it can also be optionally preceded by the standard two write decoding cycles (writing aah to 555h and 55h to aaah). it must be executed after: ? reading the flash protection status or flash id ? an error condition has occurred (and the device has set the error flag bit (dq5) to '1' during a flash memory program or erase cycle. the reset flash instruction puts the flash memo- ry back into normal read mode. if an error condi- tion has occurred (and the device has set the error flag bit (dq5) to '1' the flash memory is put back into normal read mode within a few milliseconds of the reset flash instruction having been issued. the reset flash instruction is ignored when it is is- sued during a program or bulk erase cycle of the flash memory. the reset flash instruction aborts any on-going sector erase cycle, and returns the flash memory to the normal read mode within a few milliseconds. table 62. sector protection/security bit definition ? flash protection register note: bit definitions: sec_prot 1 = primary flash memory or secondary flash memory sector is write-protected. sec_prot 0 = primary flash memory or secondary flash memory sector is not write-protected. table 63. sector protection/security bit definition ? secondary flash protection register note: bit definitions: sec_prot 1 = secondary flash memory sector is write-protected. sec_prot 0 = secondary flash memory sector is not write-protected. security_bit 0 = security bit in device has not been set; 1 = security bit in device has been set. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 security_bit not used not used not used not used not used sec1_prot sec0_prot psd3251f 84/128 sram the sram is enabled when sram select (rs0) from the dpld is high. sram select (rs0) can contain up to two product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to voltage standby (v stby , pc2). if you have an external battery connected to the psd3200, the contents of the sram are retained in the event of a power loss. the contents of the sram are re- tained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the bat- tery voltage, an internal power switchover to the battery occurs. pc4 can be configured as an output that indicates when power is being drawn from the external bat- tery. battery-on indicator (v baton , pc4) is high with the supply voltage falls below the battery volt- age and the battery on voltage standby (v stby , pc2) is supplying power to the internal sram. sram select (rs0), voltage standby (v stby , pc2) and battery-on indicator (v baton , pc4) are all configured using psdsoft express configura- tion. sector select and sram select sector select (fs0-fs3, csboot0-csboot1) and sram select (rs0) are all outputs of the dpld. they are setup by writing equations for them in psdsoft express. the following rules ap- ply to the equations for these signals: 1. primary flash memory and secondary flash memory sector select signals must not be larg- er than the physical sector size. 2. any primary flash memory sector must not be mapped in the same memory space as another flash memory sector. 3. a secondary flash memory sector must not be mapped in the same memory space as another secondary flash memory sector. 4. sram and i/o must not overlap. 5. a secondary flash memory sector may overlap a primary flash memory sector. in case of over- lap, priority is given to the secondary flash memory sector. 6. sram and i/o may overlap any other memory sector. priority is given to the sram or i/o. example. fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 always accesses the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) automatically addresses secondary flash memory segment 0. any address greater than 9fffh accesses the primary flash memory seg- ment 0. you can see that half of the primary flash memory segment 0 and one-fourth of secondary flash memory segment 0 cannot be accessed in this example. note: an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 39 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest. figure 39. priority level of memory and i/o components in the psd module level 1 sram or i /o level 2 secondary non-volatile memory level 3 primary flash memory ai07865 lowest priority highest priority 85/128 psd3251f memory select configuration in program and data spaces. the mcu core has separate ad- dress spaces for program memory and data memory. any of the memories within the psd module can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the csiop space. the vm register is set using psdsoft express to have an initial value. it can subsequently be changed by the mcu so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and pri- mary flash memory in the data space at boot-up, and secondary flash memory in the program space at boot-up, and later swap the primary and secondary flash memories. this is easily done with the vm register by using psdsoft express configuration to configure it for boot-up and hav- ing the mcu change it when desired. table 64 de- scribes the vm register. table 64. vm register note: 1. ? not used ? bits should be set to '0.' bit 7 bit 6 bit 5 bit 4 primary fl_data bit 3 secondary data bit 2 primary fl_code bit 1 secondary code bit 0 sram_code not used (1) not used (1) not used (1) 0 = rd can ? t access flash memory 0 = rd can ? t access secondary flash memory 0 = psen can ? t access flash memory 0 = psen can ? t access secondary flash memory 0 = psen can ? t access sram not used (1) not used (1) not used (1) 1 = rd access flash memory 1 = rd access secondary flash memory 1 = psen access flash memory 1 = psen access secondary flash memory 1 = psen access sram psd3251f 86/128 separate space mode. program space is sepa- rated from data space. for example, program se- lect enable (psen ) is used to access the program code from the primary flash memory, while read strobe (rd ) is used to access data from the sec- ondary flash memory, sram and i/o port blocks. this configuration requires the vm register to be set to 0ch (see figure 40). combined space modes. the program and data spaces are combined into one memory space that allows the primary flash memory, sec- ondary flash memory, and sram to be accessed by either program select enable (psen ) or read strobe (rd ). for example, to configure the prima- ry flash memory in combined space, bits b2 and b4 of the vm register are set to '1' (see figure 41). figure 40. separate space mode figure 41. combined space mode primary flash memory dpld secondary flash memory sram rs0 csboot0-1 fs0-fs3 cs cs cs oe oe rd psen oe ai07433 primary flash memory dpld secondary flash memory sram rs0 csboot0-1 fs0-fs3 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai07434 87/128 psd3251f page register the 8-bit page register increases the addressing capability of the mcu core by a factor of up to 256. the contents of the register can also be read by the mcu. the outputs of the page register (pgr0-pgr7) are inputs to the dpld decoder and can be included in the sector select (fs0- fs3, csboot0-csboot1), and sram select (rs0) equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. figure 42 shows the page register. the eight flip- flops in the register are connected to the internal data bus d0-d7. the mcu can write to or read from the page register. the page register can be accessed at address location csiop + e0h. figure 42. page register reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal psd module selects and logic pld pgr4 pgr5 pgr6 pgr7 ai05799 psd3251f 88/128 plds the plds bring programmable logic functionality to the psd. after specifying the logic for the plds in psdsoft express, the logic is pro- grammed into the device and available upon pow- er-up. table 65. dpld and cpld inputs the psd module contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few para- graphs, and in more detail in the section entitled ? decode pld (dpld), ? page 90, and the section entitled ? complex pld (cpld), ? page 91. figure 43 shows the configuration of the plds. the dpld performs address decoding for select signals for psd module components, such as memory, registers, and i/o ports. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the out- put macrocells (omc), input macrocells (imc), and the and array. the cpld can also be used to generate external chip select (ecs1) signals. the and array is used to form product terms. these product terms are specified using psdsoft. the pld input signals consist of internal mcu sig- nals and external inputs from the i/o ports. the in- put signals are shown in table 65. the turbo bit in psd module the plds can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. resetting the turbo bit to '0' (bit 3 of pmmr0) automatically places the plds into standby if no inputs are changing. turning the turbo mode off increases propagation delays while reducing power con- sumption. see the section entitled ? power man- agement, ? page 104, on how to set the turbo bit. additionally, five bits are available in pmmr2 to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. input source input name number of signals mcu address bus a15-a0 16 mcu control signals psen , rd , wr , ale 4 reset rst 1 power-down pdn 1 port b input macrocells pb7-pb0 8 port c input macrocells pc7, pc4-pc2 4 port d inputs pd1 1 page register pgr7-pgr0 8 macrocell ab feedback mcellab.fb7- fb0 8 macrocell bc feedback mcellbc.fb7- fb0 8 flash memory program status bit ready/busy 1 89/128 psd3251f figure 43. pld diagram pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select secondary non-volatile memory selects decode pld page register cpld pt alloc. macrocell alloc. mcellab mcellbc direct macrocell access from mcu data bus 12 input macrocell (port b, c) 16 output macrocell i/o ports primary flash memory selects 1 port d inputs to port b to port b or c data bus 4 8 8 2 1 1 external chip selects to port d 1 16 12 output macrocell feedback ai07866 64 64 psd3251f 90/128 decode pld (dpld) the dpld, shown in figure 44, is used for decod- ing the address for psd module and external com- ponents. the dpld can be used to generate the following decode signals: ? 4 sector select (fs0-fs3) signals for the prima- ry flash memory (three product terms each) ? 2 sector select (csboot0-csboot1) signals for the secondary flash memory (three product terms each) ? 1 internal sram select (rs0) signal (two prod- uct terms) ? 1 internal csiop select signal (selects the psd module registers) figure 44. dpld logic array note: 1. inputs from the mcu module (inputs) (12) (8) (16) (1) pdn (apd output) i /o ports (port b, c) (8) pgr0 - pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] 2 (1) (4) pd1 psen, rd, wr, ale 2 (1) (1) reset 2 rd_bsy rs0 csiop 4 primary flash memory sector selects sram select i/o decoder select csboot 0 csboot 1 fs0 3 3 3 3 3 3 2 ai07867 fs1 fs2 fs3 1 91/128 psd3251f complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate external chip select (ecs1), routed to port d. although external chip select (ecs1) can be pro- duced by any output macrocell (omc), external chip select (ecs1) on port d does not consume any output macrocells (omc). as shown in figure 43, the cpld has the following blocks: 12 input macrocells (imc) 16 output macrocells (omc) macrocell allocator product term allocator and array capable of generating up to 137 product terms four i/o ports. each of the blocks are described in the sections that follow. the input macrocells (imc) and output macrocells (omc) are connected to the psd module internal data bus and can be directly accessed by the mcu. this enables the mcu software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and array as required in most standard pld macrocell architectures. figure 45. macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input ale pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select macrocell to i/o port alloc. cpld output to other i/o ports pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai06602 psd3251f 92/128 output macrocell (omc) eight of the output macrocells (omc) are con- nected to ports b pin and are named as mcellab0- mcellab7. the other eight macrocells are connect- ed to ports b and c pins and are named as mcellbc0-mcellbc7. if an mcellbc output is not assigned to a specific pin in psdsoft, the macro- cell allocator block assigns it to either port b or c. the output macrocell (omc) architecture is shown in figure 46. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other output macrocells (omc). the polarity of the product term is controlled by the xor gate. the output macrocell (omc) can im- plement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the output macrocell (omc) block can be configured as a d, t, jk, or sr type in ps- dsoft. the flip-flop ? s clock, preset, and clear inputs may be driven from a product term of the and ar- ray. alternatively, clkin (pd1) can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. table 66. output macrocell port and data bit assignments note: 1. port pc0, pc1, pc5 and pc6 are assigned to jtag pins, and are not available as macrocell outputs output macrocell port assignment (1) native product terms maximum borrowed product terms data bit for loading or reading mcellab0 port b0 3 6 d0 mcellab1 port b1 3 6 d1 mcellab2 port b2 3 6 d2 mcellab3 port b3 3 6 d3 mcellab4 port b4 3 6 d4 mcellab5 port b5 3 6 d5 mcellab6 port b6 3 6 d6 mcellab7 port b7 3 6 d7 mcellbc0 port b0 (2) 45d0 mcellbc1 port b1 (2) 45d1 mcellbc2 port b2, c2 4 5 d2 mcellbc3 port b3, c3 4 5 d3 mcellbc4 port b4, c4 4 6 d4 mcellbc5 port b5 (2) 46d5 mcellbc6 port b6 (2) 46d6 mcellbc7 port b7, c7 4 6 d7 93/128 psd3251f product term allocator the cpld has a product term allocator. psdsoft uses the product term allocator to borrow and place product terms from one macrocell to anoth- er. the following list summarizes how product terms are allocated: mcellab0-mcellab7 all have three native product terms and may borrow up to six more mcellbc0-mcellbc3 all have four native product terms and may borrow up to five more mcellbc4-mcellbc7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. if an equation requires more product terms than are available to it, then ? external ? product terms are required, which consume other output macro- cells (omc). if external product terms are used, extra delay is added for the equation that required the extra product terms. this is called product term expansion. psdsoft express performs this expansion as needed. loading and reading the output macrocells (omc). the output macrocells (omc) block oc- cupies a memory location in the mcu address space, as defined by the csiop block (see the section entitled ? i/o ports (psd module), ? on page 95). the flip-flops in each of the 16 output macrocells (omc) can be loaded from the data bus by a mcu. loading the output macrocells (omc) with data from the mcu takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as load- able counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the output macrocells (omc) on the trailing edge of write strobe (wr , edge loading) or during the time that write strobe (wr ) is active (level loading). the method of loading is specified in psdsoft express config- uration. figure 46. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin macrocell allocator mcu data bus d [ 7:0 ] direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd macrocell cs ai06617 psd3251f 94/128 the omc mask register. there is one mask register for each of the two groups of eight output macrocells (omc). the mask registers can be used to block the loading of data to individual out- put macrocells (omc). the default value for the mask registers is 00h, which allows loading of the output macrocells (omc). when a given bit in a mask register is set to a '1,' the mcu is blocked from writing to the associated output macrocells (omc). for example, suppose mcellab0- mcellab3 are being used for a state machine. you would not want a mcu write to mcellab to over- write the state machine registers. therefore, you would want to load the mask register for mcellab (mask macrocell ab) with the value 0fh. the output enable of the omc. the output macrocells (omc) block can be connected to an i/ o port pin as a pld output. the output enable of each port pin driver is controlled by a single prod- uct term from the and array, ored with the direc- tion register output. the pin is enabled upon power-up if no output enable equation is defined and if the pin is declared as a pld output in psd- soft express. if the output macrocell (omc) output is declared as an internal node and not as a port pin output in the psdabel file, the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array. input macrocells (imc) the cpld has 12 input macrocells (imc), one for each pin on port b, and four on port c. the archi- tecture of the input macrocells (imc) is shown in figure 47. the input macrocells (imc) are individ- ually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the input macrocells (imc) can be read by the mcu through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale). each product term output is used to latch or clock four input macro- cells (imc). port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the input macrocells (imc) are specified by equations written in psdsoft (see ap- plication note an1171 ). outputs of the input mac- rocells (imc) can be read by the mcu via the imc buffer. see the section entitled ? i/o ports (psd module), ? page 95. figure 47. input macrocell output macrocells bc and macrocell ab pt pt feedback and array pld input bus port driver i/o pin mcu data bus d [ 7: 0 ] direction register mux mux ale pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai06603 95/128 psd3251f i/o ports (psd module) there are three programmable i/o ports: ports b, c, and d in the psd module. each of the ports is eight bits except port d, which is 1 bit. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are config- ured using psdsoft express configuration or by the mcu writing to on-chip registers in the csiop space. the topics discussed in this section are: general port architecture port operating modes port configuration registers (pcr) port data registers individual port functionality. general port architecture the general architecture of the i/o port block is shown in figure 48. individual port architectures are shown in figure 49 to figure 52. in general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. exceptions are noted. as shown in figure 48, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the control registers (port b only) and psdsoft express configuration. inputs to the multiplexer include the following: output data from the data out register latched address outputs cpld macrocell output external chip select (ecs1) from the cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the mcu. the data out and macrocell outputs, direc- tion and control registers, and port pin input are all connected to the port data buffer (pdb). figure 48. general i/o port architecture mcu data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai06604 psd3251f 96/128 the port pin ? s tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdsoft, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the mcu. the port data buffer (pdb) feedback path allows the mcu to check the contents of the registers. ports b and c have embedded input macrocells (imc). the input macrocells (imc) can be config- ured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by address strobe (ale) or a product term from the pld and array. the outputs from the input mac- rocells (imc) drive the pld input bus and can be read by the mcu. see the section entitled ? input macrocell, ? page 94. port operating modes the i/o ports have several modes of operation. some modes can be defined using psdsoft, some by the mcu writing to the control registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be pro- grammed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the mcu can be done so dynamically at run-time. the pld i/o, data port, and address input modes are the only modes that must be defined before programming the device. all other modes can be changed by the mcu at run-time. see application note an1171 for more detail. table 67 summarizes which modes are available on each port. table 70 shows how and where the different modes are configured. each of the port operating modes are described in the following sections. mcu i/o mode in the mcu i/o mode, the mcu uses the i/o ports block to expand its own i/o ports. by setting up the csiop space, the ports on the psd module are mapped into the mcu address space. the ad- dresses of the ports are listed in table 59. a port pin can be put into mcu i/o mode by writing a '0' to the corresponding bit in the control regis- ter. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. when the pin is configured as an output, the con- tent of the data out register drives the pin. when configured as an input, the mcu can read the port input through the data in buffer. see figure 48, page 95. ports c and d do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if equations are written for them in ps- dabel. pld i/o mode the pld i/o mode uses a port as an input to the cpld ? s input macrocells (imc), and/or as an out- put from the cpld ? s output macrocells (omc). the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by resetting the corresponding bit in the direction register to '0.' the corresponding bit in the direction register must not be set to '1' if the pin is defined for a pld input signal in psdsoft. the pld i/o mode is specified in psdsoft by declaring the port pins, and then writing an equation assigning the pld i/ o to a port. address out mode address out mode can be used to drive latched mcu addresses on to the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a '1' for pins to use address out mode. this must be done by the mcu at run-time. see table 69 for the address output pin assignments on port b. jtag in-system programming (isp) port c is jtag compliant, and can be used for in- system programming (isp). for more information on the jtag port, see the section entitled ? pro- gramming in-circuit using the jtag se- rial interface, ? page 109. 97/128 psd3251f table 67. port operating modes note: 1. jtag pins (tms, tck, tdi, tdo) are dedicated pins. 2. on pins pc2, pc3, pc4 and pc7 only. table 68. port operating mode settings note: n/a = not applicable 1. the direction of the port b, c, and d pins are controlled by the direction register ored with the individual output enable pr oduct term (.oe) from the cpld and array. table 69. i/o port latched address output assignments port configuration registers (pcr) each port has a set of port configuration regis- ters (pcr) used for configuration. the contents of the registers can be accessed by the mcu through normal read/write bus cycles at the addresses given in table 59. the addresses in table 59 are the offsets in hexadecimal from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three port configuration registers (pcr), shown in table 70, are used for setting the port configurations. the default power-up state for each register in table 70 is 00h. control register. any bit reset to '0' in the con- trol register sets the corresponding port pin to mcu i/o mode, and a '1' sets it to address out mode. the default mode is mcu i/o. only port b has an associated control register. direction register. the direction register, in conjunction with the output enable (except for port d), controls the direction of data flow in the i/o ports. any bit set to '1' in the direction register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. the de- fault mode for all port pins is input. figure 49, page 100 and figure 50, page 101 show the port architecture diagrams for ports b and c, respectively. the direction of data flow for ports b, and c are controlled not only by the direc- tion register, but also by the output enable product term from the pld and array. if the output enable product term is not active, the direction register has sole control of a given pin ? s direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in table 73. since port d only contains one pin (shown in figure 52), the direction register for port d has only one bit active. port mode port b port c port d m cu i/ o ye s yes yes pld i/o mcellab outputs mcellbc outputs additional ext. cs outputs pld inputs ye s ye s no ye s no yes (3) no yes no no yes yes address out yes (a7 ? 0) no no jtag isp no yes (1) no mode defined in psdsoft control register setting direction register setting vm register setting mcu i/o declare pins only 0 1 = output, 0 = input (note 1) n/a pld i/o logic equations n/a (note 1) n/a address out (port b) declare pins only 1 1 (note 1) n/a port b (pb3-pb0) port b (pb7-pb4) address a3-a0 address a7-a4 psd3251f 98/128 drive select register. the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a '1.' the default pin drive is cmos. note: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive reg- ister is set to '1.' the default rate is slow slew. table 74, page 99 shows the drive register for ports b, c, and d. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. table 70. port configuration registers (pcr) note: 1. see table 74 for drive register bit definition. table 71. port pin direction control, output enable p.t. not defined table 72. port pin direction control, output enable p.t. defined table 73. port direction assignment example register name port mcu access control b write/read direction b, c, d write/read drive select (1) b, c, d write/read direction register bit port pin mode 0 input 1 output direction register bit output enable p. t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1 99/128 psd3251f port data registers the port data registers, shown in table 75, are used by the mcu to write data to or read data from the ports. table 75 shows the register name, the ports having each register type, and mcu access for each register type. the registers are described below. data in. port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin in- put is read through the data in buffer. data out register. stores output data written by the mcu in the mcu i/o output mode. the con- tents of the register are driven out to the pins if the direction register or the output enable product term is set to '1.' the contents of the register can also be read back by the mcu. output macrocells (omc). the cpld output macrocells (omc) occupy a location in the mcu ? s address space. the mcu can read the output of the output macrocells (omc). if the omc mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops. see the sec- tion entitled ? plds, ? page 88. omc mask register. each omc mask register bit corresponds to an output macrocell (omc) flip- flop. when the omc mask register bit is set to a '1,' loading data into the output macrocell (omc) flip-flop is blocked. the default value is '0' or un- blocked. input macrocells (imc). the input macrocells (imc) can be used to latch or store external inputs. the outputs of the input macrocells (imc) are rout- ed to the pld input bus, and can be read by the mcu. see the section entitled ? plds, ? page 88. enable out. the enable out register can be read by the mcu. it contains the output enable values for a given port. a '1' indicates the driver is in out- put mode. a '0' indicates the driver is in tri-state and the pin is in input mode. table 74. drive register pin assignment note: 1. na = not applicable. table 75. port data registers drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port b open drain open drain open drain open drain slew rate slew rate slew rate slew rate port c open drain na (1) na (1) open drain open drain open drain na (1) na (1) port d na (1) na (1) na (1) na (1) na (1) slew rate slew rate na (1) register name port mcu access data in b, c, d read ? input on pin data out b, c, d write/read output macrocell b, c read ? outputs of macrocells write ? loading macrocells flip-flop mask macrocell b, c write/read ? prevents loading into a given macrocell input macrocell b, c read ? outputs of the input macrocells enable out b, c read ? the output enable control of the port driver psd3251f 100/128 port b ? functionality and structure port b can be configured to perform one or more of the following functions (see figure 49): mcu i/o mode cpld output ? macrocells mcellab7-mcellab0 can be connected to port b. mcellbc7- mcellbc0 can be connected to port b or port c. cpld input ? via the input macrocells (imc). latched address output ? provide latched address output as per table 69. open drain/slew rate ? pins pb3-pb0 can be configured to fast slew rate, pins pb7-pb4 can be configured to open drain mode. figure 49. port b structure mcu data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port b pin data out address a [ 7:0 ] ai07868 101/128 psd3251f port c ? functionality and structure port c can be configured to perform one or more of the following functions (see figure 50): mcu i/o mode cpld output ? mcellbc7-mcellbc0 outputs can be connected to port b or port c. cpld input ? via the input macrocells (imc) in-system programming (isp) ? jtag pins (tms, tck, tdi, tdo) are dedicated pins for device programming. (see the section entitled ? programming in-circuit using the jtag serial interface, ? page 109, for more information on jtag programming.) open drain ? port c pins can be configured in open drain mode battery backup features ? pc2 can be configured for a battery input supply, voltage standby (v stby ). pc4 can be configured as a battery-on indicator (v baton ), indicating when v cc is less than v bat . port c does not support address out mode, and therefore no control register is required. figure 50. port c structure note: 1. isp or battery back-up mcu data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term ( .oe ) read mux p d b cpld - input dir reg. input macrocell enable out special function 1 special function 1 configuration bit data in output select output mux port c pin data out ai06618 psd3251f 102/128 port d ? functionality and structure port d has only one pin, pd1. see figure 51 and figure 52. this port does not support address out mode, and therefore no control register is re- quired. of the eight bits in the port d registers, only bit 1 is used to configure pin pd1. port d can be configured to perform one or more of the following functions: mcu i/o mode cpld output ? external chip select (ecs1) cpld input ? direct input to the cpld, no input macrocells (imc) slew rate ? pins can be set up for fast slew rate port d pins can be configured in psdsoft express as input pins for other dedicated functions: clkin (pd1) as input to the macrocells flip- flops and apd counter figure 51. port d structure mcu data bus data out reg. dq dq wr wr ecs1 read mux p d b cpld - input dir reg. data in enable product term (.oe) output select output mux port d pin data out ai07871 103/128 psd3251f external chip select the cpld also provides one external chip select (ecs1) output on the port d pin that can be used to select external devices. external chip select (ecs1) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 52.) figure 52. port d external chip select signals pld input bus polarity bit pd1 pin pt1 ecs1 enable (.oe) direction register cpld and array ai07869 psd3251f 104/128 power management all psd module offers configurable power saving options. these options may be used individually or in combinations, as follows: the primary and secondary flash memory, and sram blocks are built with power management technology. in addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ? wakes up, ? changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changing ? it happens automatically. the pld sections can also achieve standby mode when its inputs are not changing, as de- scribed in the sections on the power manage- ment mode registers (pmmr). as with the power management mode, the automatic power down (apd) block allows the psd module to reduce to standby current automatically. the apd unit can also block mcu address/data signals from reaching the memories and plds. the apd unit is described in more detail in the sections entitled ? power management ? page 104. built in logic monitors the address strobe of the mcu for activity. if there is no activity for a cer- tain time period (mcu is asleep), the apd unit initiates power-down mode (if enabled). once in power-down mode, all address/data signals are blocked from reaching memory and plds, and the memories are deselected internally. this al- lows the memory and plds to remain in standby mode even if the address/data signals are changing state externally (noise, other de- vices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of standby mode, but not the memories. the pmmrs can be written by the mcu at run- time to manage power. the psd module supports ? blocking bits ? in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 56). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. figure 53. apd unit the psd module has a turbo bit in pmmr0. this bit can be set to turn the turbo mode off (the de- fault is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc cur- rent). even when inputs do change, significant power can be saved at lower frequencies (ac cur- rent), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc cur- rent component and the ac component is higher. automatic power-down (apd) unit and power- down mode. the apd unit, shown in figure 53, puts the psd module into power-down mode by monitoring the activity of address strobe (ale). if the apd unit is enabled, as soon as activity on ad- dress strobe (ale) stops, a four-bit counter starts counting. if address strobe (ale/as) remains in- active for fifteen clock periods of clkin (pd1), power-down (pdn) goes high, and the psd mod- ule enters power-down mode, as discussed next. apd en pmmr0 bit 1=1 ale reset clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface csiop select flash select sram select pd clr pd pld select ai07870 105/128 psd3251f power-down mode. by default, if you enable the apd unit, power-down mode is automatically en- abled. the device enters power-down mode if ad- dress strobe (ale) remains inactive for fifteen periods of clkin (pd1). the following should be kept in mind when the psd module is in power-down mode: ? if address strobe (ale) starts pulsing again, the psd module returns to normal operating mode. the psd module also returns to normal operat- ing mode if the reset input is high. ? the mcu address/data bus is blocked from all memory and plds. ? various signals can be blocked (prior to power- down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clkin (pd1). ? note: blocking clkin (pd1) from the plds does not block clkin (pd1) from the apd unit. ? all memories enter standby mode and are drawing standby current. however, the pld and i/o ports blocks do not go into standby mode because you don ? t want to have to wait for the logic and i/o to ? wake-up ? before their outputs can change. see table 76 for power-down mode effects on psd module ports. ? typical standby current is of the order of micro- amperes. these standby current values as- sume that there are no transitions on any pld input. other power saving options. the psd module offers other reduced power saving options that are independent of the power-down mode. except for the sram standby, they are enabled by setting bits in pmmr0 and pmmr2. figure 54. enable power-down flow chart table 76. power-down mode ? s effect on ports port function pin level mcu i/o no change pld out no change address out undefined enable apd set pmmr0 bit 1 = 1 psd module in power down mode ale idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 2 through 6. ai06609 psd3251f 106/128 pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in pmmr0 (see table 77). by setting the bit to '1,' the turbo mode is off and the plds consume the specified standby current when the inputs are not switching for an extended time of 70ns. the propagation delay time is in- creased by 10ns (for a 5v device) after the turbo bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15mhz. when the turbo bit is reset to '0' (turned on), the plds run at full power and speed. the turbo bit affects the pld ? s dc power, ac power, and prop- agation delay. when the turbo mode is off, the psd3200 input clock frequency is reduced by 5mhz from the maximum rated clock frequency. blocking mcu control signals with the bits of pmmr2 (see table 78, page 107) can further re- duce pld ac power consumption. sram standby mode (battery backup). the sram in the psd module supports a battery back- up mode in which the contents are retained in the event of a power loss. the sram has voltage standby (v stby , pc2) that can be connected to an external battery. when v cc becomes lower than v stby then the sram automatically connects to voltage standby (v stby , pc2) as a power source. the sram standby current (i stby ) is typically 0.5 a. the sram data retention voltage is 2v mini- mum. the battery-on indicator (v baton ) can be routed to pc4. this signal indicates when the v cc has dropped below v stby . input clock clkin (pd1) can be turned off, to the pld to save ac power consumption. clkin (pd1) is an input to the pld and array and the output macrocells (omc). during power-down mode, or, if clkin (pd1) is not being used as part of the pld logic equation, the clock should be disabled to save ac power. clkin (pd1) is disconnected from the pld and array or the macrocells block by setting bits 4 or 5 to a '1' in pmmr0. input control signals the psd module provides the option to turn off the mcu signals (wr , rd , psen , and address strobe (ale)) to the pld to save ac power con- sumption (see table 79, page 107). these control signals are inputs to the pld and array. during power-down mode, or, if any of them are not being used as part of the pld logic equation, these con- trol signals should be disabled to save ac power. they are disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a '1' in pmmr2. table 77. power management mode registers pmmr0 bit 0 x 0 not used, and should be set to zero. bit 1 apd enable 0 = off automatic power-down (apd) is disabled. 1 = on automatic power-down (apd) is enabled. bit 2 x 0 not used, and should be set to zero. bit 3 pld turbo 0 = on pld turbo mode is on 1 = off pld turbo mode is off, saving power. psd3200 operates at 5mhz below the maximum rated clock frequency bit 4 pld array clk 0 = on clkin (pd1) input to the pld and array is connected. every change of clkin (pd1) powers-up the pld when turbo bit is '0.' 1 = off clkin (pd1) input to pld and array is disconnected, saving power. bit 5 pld mcell clk 0 = on clkin (pd1) input to the pld macrocells is connected. 1 = off clkin (pd1) input to pld macrocells is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero. 107/128 psd3251f table 78. power management mode registers pmmr2 note: the bits of this register are cleared to zero following power-up. subsequent reset pulses do not clear the registers. table 79. apd counter operation bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 pld array wr 0 = on wr input to the pld and array is connected. 1 = off wr input to pld and array is disconnected, saving power. bit 3 pld array rd 0 = on rd input to the pld and array is connected. 1 = off rd input to pld and array is disconnected, saving power. bit 4 pld array psen 0 = on psen input to the pld and array is connected. 1 = off psen input to pld and array is disconnected, saving power. bit 5 pld array ale 0 = on ale input to the pld and array is connected. 1 = off ale input to pld and array is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero. apd enable bit ale level apd counter 0 x not counting 1 pulsing not counting 1 0 or 1 counting (generates pdn after 15 clocks) psd3251f 108/128 reset timing and device status at reset upon power-up, the psd module requires a reset (reset ) pulse of duration t nlnh-po after v cc is steady. during this period, the device loads inter- nal configurations, clears some of the registers and sets the flash memory into operating mode. after the rising edge of reset (reset ), the psd module remains in the reset mode for an addition- al period, t opr , before the first memory access is allowed. the flash memory is reset to the read mode upon power-up. sector select (fs0-fs3 and csboot0-csboot1) must all be low, write strobe (wr , cntl0) high, during power-on reset for maximum security of the data contents and to remove the possibility of a byte being writ- ten on the first edge of write strobe (wr ). any flash memory write cycle initiation is prevented automatically when v cc is below v lko . warm reset once the device is up and running, the psd mod- ule can be reset with a pulse of a much shorter du- ration, t nlnh . the same t opr period is needed before the device is operational after a warm reset . figure 55 shows the timing of the power- up and warm r eset . i/o pin, register and pld status at reset table 80 shows the i/o pin, register and pld sta- tus during power-on reset , warm reset , and power-down mode. pld outputs are always valid during warm reset , and they are valid in power- on reset once the internal configuration bits are loaded. this loading is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are de- termined by the pld equations. figure 55. reset (reset ) timing table 80. status during power-on reset , warm reset and power-down mode note: 1. the sr_cod and periphmode bits in the vm register are always cleared to '0' on power-on reset or warm reset . port configuration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined register power-on reset warm reset power-down mode pmmr0 and pmmr2 cleared to '0' unchanged unchanged macrocells flip-flop status cleared to '0' by internal power-on reset depends on .re and .pr equations depends on .re and .pr equations vm register (1) initialized, based on the selection in psdsoft configuration menu initialized, based on the selection in psdsoft configuration menu unchanged all other registers cleared to '0' cleared to '0' unchanged t nlnh-po t opr ai07437 reset t nlnh t opr v cc v cc (min) power-on reset warm reset 109/128 psd3251f programming in-circuit using the jtag serial interface the jtag serial interface pins (tms, tck, tdi, tdo) are dedicated pins on port c (see table 81). all memory blocks (primary and secondary flash memory), pld logic, and psd module configura- tion register bits may be programmed through the jtag serial interface block. a blank device can be mounted on a printed circuit board and pro- grammed using jtag. the standard jtag signals (i eee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr , are optional jtag extensions used to speed up program and erase cycles. by default, on a blank device (as shipped from the factory or after erasure), four pins on port c are the basic jtag signals tms, tck, tdi, and tdo . standard jtag signals at power-up, the standard jtag pins are inputs, waiting for a jtag serial command from an exter- nal jtag controller device (such as flashlink or automated test equipment). when the enabling command is received, tdo becomes an output and the jtag channel is fully functional. the same command that enables the jtag channel may optionally enable the two additional jtag sig- nals, tstat and terr . the reset input to the ps3200 should be active during jtag programming. the active reset puts the mcu module into reset mode while the psd module is being programmed. see applica- tion note an1153 for more details on jtag in- system programming (isp). the psd3251f device supports jtag in-sys- tem-configuration (isc) commands, but not boundary scan. the psdsoft express software tool and flashlink jtag programming cable im- plement the jtag in-system-configuration (isc) commands. table 81. jtag port signals jtag extensions tstat and terr are two jtag extension signals enabled by an ? isc_enable ? command received over the four standard jtag signals (tms, tck, tdi, and tdo). they are used to speed program and erase cycles by indicating status on pds signals instead of having to scan the status out se- rially using the standard jtag channel. see appli- cation note an1153 . terr indicates if an error has occurred when erasing a sector or programming a byte in flash memory. this signal goes low (active) when an error condition occurs, and stays low until an ? isc_clear ? command is executed or a chip re- set (reset ) pulse is received after an ? isc_disable ? command. tstat behaves the same as ready/busy de- scribed in the section entitled ? ready/busy (pc3), ? page 75. tstat is high when the psd module device is in read mode (primary and secondary flash memory contents can be read). tstat is low when flash memory program or erase cycles are in progress, and also when data is being writ- ten to the secondary flash memory. tstat and terr can be configured as ? open drain ? type signals during an ? isc_enable ? com- mand. security and flash memory protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program, erase and verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft express configuration. all primary and secondary flash memory sectors can individually be sector protected against era- sures. the sector protect bits can be set in psd- soft express configuration. initial delivery state when delivered from st, the psd3251f device have all bits in the memory and plds set to '1.' the code, configuration, and pld logic are loaded using the programming procedure. information for programming the device is available directly from st. please contact your local sales representa- tive. port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status (optional) pc4 terr error flag (optional) pc5 tdi serial data in pc6 tdo serial data out psd3251f 110/128 ac/dc parameters these tables describe the ad and dc parameters of the psd3251f device: ? dc electrical specification ? ac timing specification pld timing ? combinatorial timing ? synchronous clock mode ? asynchronous clock mode ? input macrocell timing mcu module timing ? read timing ? write timing ? power-down and reset timing the following are issues concerning the parame- ters presented: ? in the dc specification the supply current is giv- en for different modes of operation. ? the ac power component gives the pld, flash memory, and sram ma/mhz specification. fig- ure 56 shows the pld ma/mhz as a function of the number of product terms (pt) used. ? in the pld timing parameters, add the required delay when turbo bit is '0.' figure 56. pld i cc /frequency consumption (5v range) 0 10 20 30 40 60 70 80 90 100 110 v cc = 5v 50 01015 5 20 25 highest composite frequency at pld inputs (mhz) i cc ? (ma) turbo on (100%) turbo on (25%) turbo off turbo off pt 100% pt 25% ai02894 111/128 psd3251f table 82. psd module example, typ. power calculation at v cc = 5.0v (turbo mode off) conditions mcu clock frequency = 12mhz highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 2mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 40% % power-down mode = 60% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = off calculation (using typical values) i cc total = i cc (mcuactive) x %mcuactive + i cc (psdactive) x %psdactive + i pd (pwrdown) x %pwrdown i cc (mcuactive) = 20ma i pd (pwrdown) = 250a i cc (psdactive) = i cc (ac) + i cc (dc) = %flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld) = 0.8 x 2.5 ma/mhz x 2mhz + 0.15 x 1.5 ma/mhz x 2mhz + 24 ma = (4 + 0.45 + 24) ma = 28.45ma i cc total = 20ma x 40% + 28.45ma x 40% + 250a x 60% = 8ma + 11.38ma + 150a = 19.53ma this is the operating power with no flash memory erase or program cycles in progress. calculation is based on all i/ o pins being disconnected and i out = 0 ma. psd3251f 112/128 maximum rating stressing the device above the rating listed in the absolute maximum ratings ? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 83. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100pf, r1=1500 ? , r2=500 ? ) dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 84. operating conditions (5v device) symbol parameter min. max. unit t stg storage temperature ? 65 125 c t lead lead temperature during soldering (20 seconds max.) (1) 235 c v io input and output voltage (q = v oh or hi-z) ? 0.5 6.5 v v cc supply voltage ? 0.5 6.5 v v pp device programmer supply voltage ? 0.5 14.0 v v esd electrostatic discharge voltage (human body model) 2 ? 2000 2000 v symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (industrial) ? 40 85 c ambient operating temperature (commercial) 0 70 c 113/128 psd3251f table 85. ac symbols for timing example: t avlx ? time from address valid to ale invalid. figure 57. switching waveforms ? key signal letters signal behavior a address t time c clock l logic level low or ale d input data h logic level high i instruction v valid l ale x no longer a valid logic level n reset input or output z float p psen signal pw pulse width q output data r rd signal w wr signal b v stby output m output macrocell waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102 psd3251f 114/128 table 86. dc characteristics (5v device) symbol parameter test condition (in addition to those in table 84, page 112) min. typ. max. unit v ih input high voltage (ports 1, 3, 4[bits 7,6,5,4,3,1,0], xtal1, reset ) 4.5v < v cc < 5.5v 0.7v cc v cc + 0.5 v v ih1 input high voltage (ports b, c, d, 4[bit 2]) 4.5v < v cc < 5.5v 2.0 v cc + 0.5 v v il input low voltage (ports 1, 3, 4[bits 7,6,5,4,3,1,0], xtal1, reset ) 4.5v < v cc < 5.5v v ss ? 0.5 0.3v cc v v il1 input low voltage (ports b, c, d) 4.5v < v cc < 5.5v ? 0.5 0.8 v input low voltage (port 4[bit 2]) 4.5v < v cc < 5.5v v ss ? 0.5 0.8 v v ol output low voltage (ports b, c, d) i ol = 20a v cc = 4.5v 0.01 0.1 v i ol = 8ma v cc = 4.5v 0.25 0.45 v v ol1 output low voltage (ports 1,3,4) i ol = 1.6ma 0.45 v v oh output high voltage (ports b, c, d) i oh = ? 20a v cc = 4.5v 4.4 4.49 v i oh = ? 2ma v cc = 4.5v 2.4 3.9 v v oh1 output high voltage (ports 1,3,4) i oh = ? 80a 2.4 v i oh = ? 10a 4.05 v v oh3 output high voltage v stbyon i oh = ? 1a v stby ? 0.8 v v lvr low voltage reset 0.1v hysteresis 3.75 4.0 4.25 v v op xtal open bias voltage (xtal1, xtal2) i ol = 3.2ma 2.0 3.0 v v lko v cc (min) for flash erase and program 2.5 4.2 v v stby sram (psd) standby voltage 2.0 v cc ? 0.2 v v df sram (psd) data retention voltage only on v stby 2v i il logic '0' input current (ports 1,3,4) v in = 0.45v (0v for port 4[pin 2]) ? 10 ? 50 a i tl logic 1-to-0 transition current (ports 1,3,4) v in = 3.5v (2.5v for port 4[pin 2]) ? 65 ? 650 a i stby sram (psd) standby current (v stby input) v cc = 0v 0.5 1 a i idle sram (psd) idle current (v stby input) v cc > v stby ? 0.1 0.1 a 115/128 psd3251f note: 1. i pd (power-down mode) is measured with: xtal1=v ss ; xtal2=not connected; reset =v cc ; all other pins are disconnected. pld not in turbo mode. 2. i cc_cpu (active mode) is measured with: xtal1 driven with t clch , t chcl = 5ns, v il = v ss +0.5v, v ih = vcc ? 0.5v, xtal2 = not connected; reset =v ss ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (approximately 1ma). 3. i cc_cpu (idle mode) is measured with: xtal1 driven with t clch , t chcl = 5ns, v il = v ss +0.5v, v ih = v cc ? 0.5v, xtal2 = not connected; reset =v cc ; all other pins are disconnected. 4. see figure 56 for the pld current calculation. 5. i/o current = 0 ma, all i/o pins are disconnected. i rst reset pin pull-up current (reset ) v in = v ss ? 10 ? 55 a i fr xtal feedback resistor current (xtal1) xtal1 = v cc xtal2 = v ss ? 20 ? 50 a i li input leakage current v ss < v in < v cc ? 11 a i lo output leakage current 0.45 < v out < v cc ? 10 10 a i pd (1) power-down mode v cc = 5.5v lvd logic disabled 250 a lvd logic enabled 380 a i cc_cpu (2,3,5) active (12mhz) v cc = 5v 20 30 ma idle (12mhz) 8 10 ma active (24mhz) v cc = 5v 30 38 ma idle (24mhz) 15 20 ma active (40mhz) v cc = 5v 40 62 ma idle (40mhz) 20 30 ma i cc_psd (dc) (5) operating supply current pld only pld_turbo = off, f = 0mhz (4) 0 a/pt (5) pld_turbo = on, f = 0mhz 400 700 a/pt flash memory during flash memory write/erase only 15 30 ma read only, f = 0mhz 0 0 ma sram f = 0mhz 0 0 ma i cc_psd (ac) (5) pld ac base note 4 flash memory ac adder 2.5 3.5 ma/ mhz sram ac adder 1.5 3.0 ma/ mhz symbol parameter test condition (in addition to those in table 84, page 112) min. typ. max. unit psd3251f 116/128 table 87. external clock drive (with the 5v mcu module) note: 1. conditions (in addition to those in table 84, v cc = 4.5 to 5.5v): v ss = 0v; c l for ale and psen output is 100pf; c l for other outputs is 80pf table 88. a/d analog specification symbol parameter (1) 40mhz oscillator variable oscillator 1/t clcl = 24 to 40mhz unit min max min max t rlrh oscillator period 25 41.7 ns t wlwh high time 10 t clcl ? t clcx ns t llax2 low time 10 t clcl ? t clcx ns t rhdx rise time 10 ns t rhdx fall time 10 ns symbol parameter test condition min. typ. max. unit av ref analog power supply input voltage range v ss v cc v v an analog input voltage range v ss ? 0.3 av ref + 0.3 v i avdd current following between v cc and v ss 200 a ca in overall accuracy 2 l.s.b. n nle non-linearity error 2 l.s.b. n dnle differential non-linearity error 2 l.s.b. n zoe zero-offset error 2 l.s.b. n fse full scale error 2 l.s.b. n ge gain error 2 l.s.b. t conv conversion time at 8mhz clock 20 s 117/128 psd3251f figure 58. input to output disable / enable table 89. cpld combinatorial timing (5v device) note: 1. fast slew rate output available on pb3-pb0 and pd1. decrement times by given amount. 2. t pd for mcu address and control signals refers to delay from pins on mcu bus to cpld combinatorial output. symbol parameter conditions min max pt aloc tu rbo off slew rate (1) unit t pd (2) cpld input pin/feedback to cpld combinatorial output 20 + 2 + 10 ? 2ns t ea cpld input to cpld output enable 21 + 10 ? 2ns t er cpld input to cpld output disable 21 + 10 ? 2ns t arp cpld register clear or preset delay 21 + 10 ? 2ns t arpw cpld register clear or preset pulse width 10 + 10 ns t ard cpld array delay any macrocell 11 + 2 ns ter tea input input to output enable/disable ai02863 psd3251f 118/128 figure 59. synchronous clock mode timing ? pld table 90. cpld macrocell synchronous clock mode timing (5v device) note: 1. fast slew rate output available on pb3-pb0 and pd1. decrement times by given amount. 2. clkin (pd1) t clcl = t ch + t cl . symbol parameter conditions min max pt aloc tu rbo off slew rate (1) unit f max maximum frequency external feedback 1/(t s +t co ) 40.0 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co ? 10) 66.6 mhz maximum frequency pipelined data 1/(t ch +t cl ) 83.3 mhz t s input setup time 12 + 2 + 10 ns t h input hold time 0 ns t ch clock high time clock input 6 ns t cl clock low time clock input 6 ns t co clock to output delay clock input 13 ? 2ns t ard cpld array delay any macrocell 11 + 2 ns t min minimum clock period (2) t ch +t cl 12 ns t ch t cl t co t h t s clkin input registered output ai02860 119/128 psd3251f figure 60. asynchronous reset / preset figure 61. asynchronous clock mode timing (product term clock) table 91. cpld macrocell asynchronous clock mode timing (5v device) symbol parameter conditions min max pt aloc tu rbo off slew rate unit f maxa maximum frequency external feedback 1/(t sa +t coa ) 38.4 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa ? 10) 62.5 mhz maximum frequency pipelined data 1/(t cha +t cla ) 71.4 mhz t sa input setup time 7 + 2 + 10 ns t ha input hold time 8 ns t cha clock input high time 9 + 10 ns t cla clock input low time 9 + 10 ns t coa clock to output delay 21 + 10 ? 2ns t arda cpld array delay any macrocell 11 + 2 ns t mina minimum clock period 1/f cnta 16 ns tarp register output tarpw reset/preset input ai02864 tcha tcla tcoa tha tsa clock input registered output ai02859 psd3251f 120/128 figure 62. input macrocell timing (product term clock) table 92. input macrocell timing (5v device) note: 1. inputs from port b and c relative to register/ latch clock from the pld. ale/as latch timings refer to t avlx and t lxax . table 93. program, write and erase times (5v device) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid t q7vqv time units before the data byte, dq0-dq7, is valid for reading. symbol parameter conditions min max pt aloc turbo off unit t is input setup time (note 1) 0ns t ih input hold time (note 1) 15 + 10 ns t inh nib input high time (note 1) 9ns t inl nib input low time (note 1) 9ns t ino nib input to combinatorial delay (note 1) 34 + 2 + 10 ns symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase (1) (pre-programmed) 330s flash bulk erase (not pre-programmed) 5 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 150 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) (2) 30 ns t inh t inl t ino t ih t is pt clock input output ai03101 121/128 psd3251f figure 63. reset (reset ) timing table 94. reset (r eset ) timing (5v device) note: 1. reset (reset ) does not reset flash memory program or erase cycles. table 95. v stbyon definitions timing (5v device) note: 1. v stbyon timing is measured at v cc ramp rate of 2ms. symbol parameter conditions min max unit t nlnh reset active low time (1) 150 ns t nlnh ? po power-on reset active low time 1 ms t opr reset high to operational device 120 ns symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1) 20 s t bxbl v stby off detection to v stbyon output low (note 1) 20 s t nlnh-po t opr ai07437 reset t nlnh t opr v cc v cc (min) power-on reset warm reset psd3251f 122/128 figure 64. isc timing table 96. isc timing (5v device) note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter conditions min max unit t isccf clock (tck, pc1) frequency (except for pld) (note 1) 20 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1) 23 ns t isccl clock (tck, pc1) low time (except for pld) (note 1) 23 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2) 2mhz t iscchp clock (tck, pc1) high time (pld only) (note 2) 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2) 240 ns t iscpsu isc port set up time 7 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 21 ns t iscpzv isc port high-impedance to valid output 21 ns t iscpvz isc port valid output to high-impedance 21 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865 123/128 psd3251f figure 65. mcu module ac measurement i/o waveform note: ac inputs during testing are driven at v cc ? 0.5v for a logic '1,' and 0.45v for a logic '0.' timing measurements are made at v ih (min) for a logic '1,' and v il (max) for a logic '0' figure 66. psd module ac float i/o waveform note: for timing purposes, a port pin is considered to be no longer floating when a 100mv change from load voltage occurs, and b egins to float when a 100mv change from the loaded v oh or v ol level occurs i ol and i oh 20ma figure 67. external clock cycle figure 68. recommended oscillator circuits note: c1, c2 = 30pf 10pf for crystals for ceramic resonators, contact resonator manufacturer oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and cerami c resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. ai06650 v cc ? 0.5v 0.45v test points 0.2 v cc ? 0.1v 0.2 v cc + 0.9v ai06651 test reference points v ol + 0.1v v oh ? 0.1v v load ? 0.1v v load + 0.1v 0.2 v cc ? 0.1v psd3251f 124/128 figure 69. psd module ac measurement i/o waveform figure 70. psd module ac measurement load circuit table 97. capacitance note: sampled only, not 100% tested. 1. typical values are for t a = 25 c and nominal supply voltages. 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 ? c l = 30 pf (including scope and jig capacitance) ai03104b symbol parameter test condition typ . (1) max . unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf 125/128 psd3251f package mechanical information figure 71. tqfp52 ? 52-lead plastic quad flatpack package outline note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 d1 d 1 e ne c d2 e2 l1 psd3251f 126/128 table 98. tqfp52 ? 52-lead plastic quad flatpack package mechanical data symb mm inches typ min max typ min max a ?? 1.75 ?? 0.069 a1 ? 0.05 0.020 ? 0.002 0.008 a2 ? 1.25 1.55 ? 0.049 0.061 b ? 0.02 0.04 ? 0.007 0.016 c ? 0.07 0.23 ? 0.002 0.009 d 12.00 ?? 0.473 ?? d1 10.00 ?? 0.394 ?? d2 e 12.00 ?? 0.473 ?? e1 10.00 ?? 0.394 ?? e2 e0.65 ?? 0.026 ?? l ? 0.45 0.75 ? 0.018 0.030 l1 1.00 ?? 0.039 ?? ? 0 7 ? 0 7 n52 52 nd 13 13 ne 13 13 cp ?? 0.10 ?? 0.004 127/128 psd3251f revision history table 99. document revision history date rev. # revision details june 2003 1.0 first issue psd3251f 128/128 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com |
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